A self-assembled nanostructure comprises first domains and second domains. The first domains comprise a first block of a block copolymer material and an activatable catalyst. The second domains comprise a second block and substantially without the activatable catalyst. The activatable catalyst is capable of generating catalyst upon application of activation energy, and the generated catalyst is capable of reacting with a metal oxide precursor to provide a metal oxide. A semiconductor structure comprises such self-assembled nanostructure on a substrate.

A novel deposition method of a metal oxide is provided. The deposition method includes a first step of supplying a first precursor to a chamber; a second step of supplying a second precursor to the chamber; a third step of supplying a third precursor to the chamber; and a fourth step of introducing an oxidizer into the chamber after the first step, the second step, and the third step. The first to third precursors are different kinds of precursors, and a substrate placed in the chamber in the first to fourth steps is heated to a temperature higher than or equal to 300° C. and lower than or equal to decomposition temperatures of the first to third precursors.

Disclosed are a thin-film transistor and a preparation method therefor, and a display substrate and a display panel. The thin-film transistor includes: a base substrate; an active layer located on the base substrate; and a source-drain electrode which is located on the side of the active layer facing away from the base substrate, and includes an electrode layer and a protective layer, where the material of the electrode layer includes a first metal element; the protective layer covers the surface of the side of the electrode layer facing away from the base substrate, and a side face of the electrode layer; and the material of the protective layer is an oxide of the first metal element.

A method and system for forming material within a gap on a surface of a substrate are disclosed. An exemplary method includes forming a material layer on a surface of the substrate within a first reaction chamber, exposing the material layer to a halogen reactant in a second reaction chamber to thereby form a flowable layer comprising a halogen within the gap, and optionally exposing the flowable layer to a converting reactant in a third reaction chamber to form a converted material within the gap. Exemplary methods can further include a step of heat treating the flowable layer or the converted material. Exemplary systems can perform the method.

Provided are a graphene interconnect structure, an electronic device including the graphene interconnect structure, and a method of manufacturing the graphene interconnect structure. The graphene interconnect structure may include: a first oxide dielectric material layer; a second oxide dielectric material layer on a surface of the first oxide dielectric material layer and having a dielectric constant greater than that of the first oxide dielectric material layer; and a graphene layer on a surface of the second oxide dielectric material layer opposite to the surface on which the first oxide dielectric material layer is located.

A boron nitride layer and a method of fabricating the same are provided. The boron nitride layer includes a boron nitride compound and has a dielectric constant of about 2.5 or less at an operating frequency of 100 kHz.

Exemplary semiconductor processing methods may include providing a boron-containing precursor and a nitrogen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include forming a plasma of the boron-containing precursor and the nitrogen-containing precursor in the processing region. A temperature of the substrate may be maintained at less than or about 500° C. The methods may include forming a layer of material on the substrate. The layer of material may include hexagonal boron nitride. The methods include subsequent forming the layer of material on the substrate for a first period of time, halting delivery of the boron-containing precursor. The methods may include maintaining a flow of the nitrogen-containing precursor for a second period of time, and increasing a plasma power while maintaining the flow of the nitrogen-containing precursor.

A microelectronic device on a semiconductor substrate comprises: a gate electrode; and a spacer adjacent to the gate electrode, the spacer comprising: a the low-k dielectric film comprising one or more species of vanadium oxide, which is optionally doped, and an optional silicon nitride or oxide film. Methods comprise depositing a low-k dielectric film optionally sandwiched by a silicon nitride or oxide film to form a spacer adjacent to a gate electrode of a microelectronic device on a semiconductor substrate, wherein the low-k dielectric film comprises a vanadium-containing film.

A method is presented for selective deposition on metals using porous low-k materials. The method includes forming alternating layers of a porous dielectric material and a first conductive material, forming a surface aligned monolayer (SAM) over the first conductive material, depositing hydroxamic acid (HA) material over the porous dielectric material, growing an oxide material over the first conductive material, removing the SAM, depositing a dielectric layer adjacent the oxide material, and replacing the oxide material with a second conductive material defining a bottom electrode.

The present disclosure describes epitaxial oxide high electron mobility transistors (HEMTs). In some embodiments, a HEMT comprises: a substrate; a first epitaxial semiconductor layer on the substrate; and a second epitaxial semiconductor layer on the first epitaxial semiconductor layer. The first epitaxial semiconductor layer can comprise a first oxide material, wherein the first oxide material can comprise a first polar material with an orthorhombic, tetragonal or trigonal crystal symmetry, and wherein the first oxide material can comprise a first conductivity type formed via polarization. The second epitaxial semiconductor layer can comprise a second oxide material.