Patent classifications
H01L21/02197
Semiconductor device and method of manufacturing the same
A semiconductor device includes a capacitor including a lower electrode an upper electrode, and a dielectric layer between the lower electrode and the upper electrode. The lower electrode includes ABO.sub.3 where ‘A’ is a first metal element and ‘B’ is a second metal element having a work function greater than that of the first metal element. The dielectric layer includes CDO.sub.3 where ‘C’ is a third metal element and ‘D’ is a fourth metal element. The lower electrode includes a first layer and a second layer which are alternately and repeatedly stacked. The first layer includes the first metal element and oxygen. The second layer includes the second metal element and oxygen. The dielectric layer is in contact with the lower electrode at a first contact surface the first contact surface corresponding to the second layer.
Common mode compensation for non-linear polar material based differential memory bit-cell
To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.
Common mode compensation for multi-element non-linear polar material based gain memory bit-cell
To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.
Capacitor including perovskite material, semiconductor device including the capacitor, and method of manufacturing the capacitor
A capacitor includes a lower electrode, a first dielectric layer provided on the lower electrode including a perovskite structure, an upper electrode including a perovskite structure, a first dielectric layer between provided on the lower electrode and the upper electrode; and a second dielectric layer, having a band gap energy greater than that of the first dielectric layer, provided between on the first dielectric layer and the upper electrode, the capacitor may have a low leakage current density and stable crystallinity, thereby suppressing a decrease in a dielectric constant.
SEMICONDUCTOR ACUPUNCTURE DEVICE AND METHOD OF USE
Semiconductor electroacupuncture needles are disclosed, as well methods of making and using the semiconductor electroacupuncture needles. A controller for controlling the characteristics of the voltage applied to the needles and/or the current flowing through the needles is described. In some embodiments, a portion of the electro acupuncture needle is insulated to control the position below the skin at which the current enters the patient. In some embodiments, an LED on the needle lights when current above a threshold value is passing through the needle and into the patient.
High-density low voltage non-volatile memory with unidirectional plate-line and bit-line and pillar capacitor
Described is a low power, high-density a 1T-1C (one transistor and one capacitor) memory bit-cell, wherein the capacitor comprises a pillar structure having ferroelectric material (perovskite, improper ferroelectric, or hexagonal ferroelectric) and conductive oxides as electrodes. In various embodiments, one layer of the conductive oxide electrode wraps around the pillar capacitor, and forms the outer electrode of the pillar capacitor. The core of the pillar capacitor can take various forms.
High-density low voltage non-volatile memory with unidirectional plate-line and bit-line and pillar capacitor
Described is a low power, high-density a 1T-1C (one transistor and one capacitor) memory bit-cell, wherein the capacitor comprises a pillar structure having ferroelectric material (perovskite, improper ferroelectric, or hexagonal ferroelectric) and conductive oxides as electrodes. In various embodiments, one layer of the conductive oxide electrode wraps around the pillar capacitor, and forms the outer electrode of the pillar capacitor. The core of the pillar capacitor can take various forms.
CAPACITOR INCLUDING PEROVSKITE MATERIAL, SEMICONDUCTOR DEVICE INCLUDING THE CAPACITOR, AND METHOD OF MANUFACTURING THE CAPACITOR
A capacitor includes a lower electrode, a first dielectric layer provided on the lower electrode including a perovskite structure, an upper electrode including a perovskite structure, a first dielectric layer between provided on the lower electrode and the upper electrode; and a second dielectric layer, having a band gap energy greater than that of the first dielectric layer, provided between on the first dielectric layer and the upper electrode, the capacitor may have a low leakage current density and stable crystallinity, thereby suppressing a decrease in a dielectric constant.
CAPACITOR INCLUDING PEROVSKITE MATERIAL, SEMICONDUCTOR DEVICE INCLUDING THE CAPACITOR, AND METHOD OF MANUFACTURING THE CAPACITOR
A capacitor includes a lower electrode, a first dielectric layer provided on the lower electrode including a perovskite structure, an upper electrode including a perovskite structure, a first dielectric layer between provided on the lower electrode and the upper electrode; and a second dielectric layer, having a band gap energy greater than that of the first dielectric layer, provided between on the first dielectric layer and the upper electrode, the capacitor may have a low leakage current density and stable crystallinity, thereby suppressing a decrease in a dielectric constant.
Method and apparatus for a thin film dielectric stack
A system that incorporates teachings of the subject disclosure may include, for example, a thin film capacitor a silicon substrate having a silicon dioxide layer; an adhesion layer on the silicon dioxide layer, wherein the adhesion layer is a polar dielectric; a first electrode layer on the adhesion layer; a dielectric layer on the first electrode layer; and a second electrode layer on the dielectric layer. Other embodiments are disclosed.