Patent classifications
H01L21/02211
OXIDE-NITRIDE-OXIDE STACK HAVING MULTIPLE OXYNITRIDE LAYERS
A semiconductor device including an oxide-nitride-oxide (ONO) structure having a multi-layer charge storing layer and methods of forming the same are provided. Generally, the method involves: (i) forming a first oxide layer of the ONO structure; (ii) forming a multi-layer charge storing layer comprising nitride on a surface of the first oxide layer; and (iii) forming a second oxide layer of the ONO structure on a surface of the multi-layer charge storing layer. Preferably, the charge storing layer comprises at least two silicon oxynitride layers having differing stoichiometric compositions of Oxygen, Nitrogen and/or Silicon. More preferably, the ONO structure is part of a silicon-oxide-nitride-oxide-silicon (SONOS) structure and the semiconductor device is a SONOS memory transistor. Other embodiments are also disclosed.
PLASMA GENERATING DEVICE, SUBSTRATE PROCESSING APPARATUS, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
There is provided a substrate processing apparatus that includes a process chamber in which at least one substrate is processed; a gas supplier configured to supply a gas; and a buffer structure. The buffer structure includes at least two plasma generation regions in which gas is converted into plasma by a pair of electrodes connected to a high-frequency power supply and an electrode to be grounded, a first gas supply port that supplies a gas generated in a first plasma generation region among the at least two plasma generation regions, and a second gas supply port that supplies a gas generated in a second plasma generation region among the at least two plasma generation regions.
Methods for depositing blocking layers on conductive surfaces
Methods of selectively depositing blocking layers on conductive surfaces over dielectric surfaces are described. In some embodiments, a 4-8 membered substituted heterocycle is exposed to a substrate to selectively form a blocking layer. In some embodiments, a layer is selectively deposited on the dielectric surface after the blocking layer is formed. In some embodiments, the blocking layer is removed.
SUBSTRATE PROCESSING APPARATUS, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM AND INNER TUBE
There is provided a substrate processing apparatus including: an inner tube including a substrate accommodating region where substrates are accommodated along an arrangement direction; an outer tube outside the inner tube; gas supply ports provided on a side wall of the inner tube along the arrangement direction; first exhaust ports provided on the side wall of the inner tube along the arrangement direction; a second exhaust port provided at an end portion of the outer tube along the arrangement direction; and a gas guide controlling gas flow in an annular space between the inner and outer tubes. A first exhaust port A is located farthest from the second exhaust port, and faces a gas supply port A. The gas guide includes a fin provided near the gas supply port A and surrounds at least a part of an outer periphery of the gas supply port A.
Method of processing substrate, method of manufacturing semiconductor device, substrate processing apparatus, and recording medium
Provided is processing of a substrate including: forming film on substrate by performing cycle, multiple times, including non-simultaneously performing: (a) supplying precursor gas and inert gas to the substrate; and (b) supplying reaction gas to the substrate. In (a), at least one of the precursor and inert gas stored in first tank is supplied to the substrate, and at least one of the precursor and inert gas stored in second tank is supplied to the substrate. A concentration of the precursor gas in the first tank differs from that in the second tank. Further, in (a), the at least one of the precursor and inert gas is supplied from the first tank to the substrate, and the at least one of the precursor and inert gas is supplied from the second tank to the substrate to suppress multiple adsorption of molecules constituting the precursor gas on the substrate's surface.
Semiconductor device
A method for fabricating a semiconductor device includes forming a first wiring layer, the first wiring layer including a first metal wiring and a first interlayer insulating film wrapping the first metal wiring on a substrate, forming a first via layer, the first via layer including a first via that is in electrical connection with the first metal wiring, and a second interlayer insulating film wrapping the first via on the first wiring layer, and forming a second wiring layer, the second wiring layer including a second metal wiring that is in electrical connection with the first via, and a third interlayer insulating film wrapping the second metal wiring on the first via layer, wherein the third interlayer insulating film contains deuterium and is formed through chemical vapor deposition using a first gas containing deuterium and a second gas containing hydrogen.
Self-alignment etching of interconnect layers
A method for etching a metal containing feature is provided. Using a pattern mask, layers of material are etched to expose a portion of a metal containing feature. At least a portion of the exposed metal containing feature is etched, and is replaced by the growth of a filler dielectric. The etched portion of the metal containing feature and the filler dielectric reduce the unwanted conductivity between adjacent metal containing features.
Nitrogen-rich silicon nitride films for thin film transistors
Embodiments of the present disclosure generally relate to nitrogen-rich silicon nitride and methods for depositing the same, and transistors and other devices containing the same. In one or more embodiments, methods for depositing silicon nitride materials are provided and include heating a workpiece to a temperature of about 200° C. to about 250° C., exposing the workpiece to a deposition gas during a plasma-enhanced chemical vapor deposition process, and depositing a nitrogen-rich silicon nitride layer on the workpiece. The deposition gas contains a silicon precursor, a nitrogen precursor, and a carrier gas. A molar ratio of the silicon precursor to the nitrogen precursor to the carrier gas within the deposition gas is about 1:a range from about 4 to about 8:a range from about 20 to about 80, respectively.
Transistor Isolation Regions and Methods of Forming the Same
In an embodiment, a device includes: an isolation region on a substrate; a first semiconductor fin protruding above the isolation region; a second semiconductor fin protruding above the isolation region; and a dielectric fin between the first semiconductor fin and the second semiconductor fin, the dielectric fin protruding above the isolation region, the dielectric fin including: a first layer including a first dielectric material having a first carbon concentration; and a second layer on the first layer, the second layer including a second dielectric material having a second carbon concentration, the second carbon concentration greater than the first carbon concentration.
METHODS AND APPARATUS FOR SELECTIVE ETCH STOP CAPPING AND SELECTIVE VIA OPEN FOR FULLY LANDED VIA ON UNDERLYING METAL
Methods and apparatus for processing a substrate are provided herein. For example, a method of processing a substrate comprises a) removing oxide from a metal layer disposed in a dielectric layer on the substrate disposed in a processing chamber, b) selectively depositing a self-assembled monolayer (SAM) on the metal layer using atomic layer deposition, c) depositing a precursor while supplying water to form one of an aluminum oxide (AlO) layer on the dielectric layer or a low-k dielectric layer on the dielectric layer, d) supplying at least one of hydrogen (H.sub.2) or ammonia (NH.sub.3) to remove the self-assembled monolayer (SAM), and e) depositing one of a silicon oxycarbonitride (SiOCN) layer or a silicon nitride (SiN) layer atop the metal layer and the one of the aluminum oxide (AlO) layer on the dielectric layer or the low-k dielectric layer on the dielectric layer.