An integrated capacitor on a semiconductor surface on a substrate includes a capacitor dielectric layer including at least one silicon compound material layer on a bottom plate. The capacitor dielectric layer includes a pitted sloped dielectric sidewall. Each of the pits is at least partially filled by one of a plurality of noncontiguous dielectric portions. A conformal dielectric layer may be formed over the noncontiguous dielectric portions. A top metal layer provides a top plate of the capacitor.

A method of forming an integrated capacitor on a semiconductor surface on a substrate includes etching a capacitor dielectric layer including at least one silicon compound material layer on a bottom plate which is above and electrically isolated from the semiconductor surface to provide at least one defined dielectric feature having sloped dielectric sidewall portion. A dielectric layer is deposited to at least partially fill pits in the sloped dielectric sidewall portion to smooth a surface of the sloped dielectric sidewall portion. The dielectric layer is etched, and a top plate is then formed on top of the dielectric feature.

A method of forming a silicon oxycarbonitride layer on a substrate is disclosed. An exemplary method includes forming a layer comprising SiOC and forming a layer comprising SiCN, which together form the silicon oxycarbonitride layer.

Disclosed are methods and systems for forming a silicon-containing layer on a substrate. The methods comprise executing a plurality of deposition cycles. A deposition cycle comprises a silicon precursor pulse that comprises exposing the substrate to a silicon precursor. The silicon precursor comprises silicon and one or more of a group 13 element and a group 15 element. A deposition cycle further comprises a plasma pulse that comprises exposing the substrate to a plasma treatment. The plasma treatment comprises generating a plasma.

The disclosure relates to an electronic device including a housing filled to a fill level with a first matrix produced from a first potting compound, and a circuit board having a component arranged thereon and having a passageway that connects a component side arranged within the housing interior filled with the first matrix and a front face of the component arranged outside the housing interior filled with the first matrix, the passageway acts as capillaries for media whose viscosity is less than a limit and as barriers for media whose viscosity is greater than the limit, the component is arranged in a spatially bounded region adjoining the component side, a second matrix produced from a second potting compound having a viscosity exceeding the limit, which second matrix effects a terminal sealing of the connection formed by the passageway against the first potting compound used for producing the first matrix.

Methods are provided for selective film deposition. One method includes providing a substrate containing a dielectric material and a metal layer, the metal layer having an oxidized metal layer thereon, coating the substrate with a metal-containing catalyst layer, treating the substrate with an alcohol solution that removes the oxidized metal layer from the metal layer along with the metal-containing catalyst layer on the oxidized metal layer, and exposing the substrate to a process gas containing a silanol gas for a time period that selectively deposits a SiO.sub.2 film on the metal-containing catalyst layer on the dielectric material.

A method of manufacturing a semiconductor device includes depositing a first insulation film in a via hole of a semiconductor substrate and above a first surface thereof, the semiconductor substrate having a circuit substrate on a second surface thereof, depositing a second insulation film having a covering property lower than the first insulation film in the via hole and above the first surface, and removing the first and second insulation films deposited at the bottom of the via hole by anisotropic etching.

Methods are provided for selective film deposition. One method includes providing a substrate containing a dielectric material and a metal layer, the metal layer having an oxidized metal layer thereon, coating the substrate with a metal-containing catalyst layer, treating the substrate with an alcohol solution that removes the oxidized metal layer from the metal layer along with the metal-containing catalyst layer on the oxidized metal layer, and exposing the substrate to a process gas containing a silanol gas for a time period that selectively deposits a SiO.sub.2 film on the metal-containing catalyst layer on the dielectric material.

A method and composition for producing a porous low k dielectric film via chemical vapor deposition is provided. In one aspect, the method comprises the steps of: providing a substrate within a reaction chamber; introducing into the reaction chamber gaseous reagents including at least one structure-forming precursor comprising a alkoxysilacyclic or acyloxysilacyclic compound with or without a porogen; applying energy to the gaseous reagents in the reaction chamber to induce reaction of the gaseous reagents to deposit a preliminary film on the substrate, wherein the preliminary film contains the porogen, and the preliminary film is deposited; and removing from the preliminary film at least a portion of the porogen contained therein and provide the film with pores and a dielectric constant of 3.2 or less. In certain embodiments, the structure-forming precursor further comprises a hardening additive.

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. The alternating stack includes a first region in which all layers of the alternating stack are present and a second region in which at least a topmost one of the electrically conductive layers is absent. First memory opening fill structures extend through the first region of the alternating stack, and second memory opening fill structures extend through the second region of the alternating stack. The first memory opening fill structures have a greater height than the second memory opening fill structures. Pocket doping regions extending over a respective subset of topmost electrically conductive layers for the memory opening fill structures can be formed to provide higher threshold voltages and to enable selective activation of vertical semiconductor channels connected a same bit line.