A semiconductor device includes a substrate having at least a trench formed therein. A conductive material fills a lower portion of the trench. A barrier layer is between the conductive material and the substrate. An insulating layer is in the trench and completely covers the conductive material and the barrier layer, wherein a portion of the insulating layer covering the barrier layer has a bird's peak profile.

A semiconductor processing system is provided to form a capacitor dielectric layer in a metal-insulator-metal capacitor. The semiconductor processing system includes a precursor tank configured to generate a precursor gas from a metal organic solid precursor, a processing chamber configured to perform a plasma enhanced chemical vapor deposition, and at least one buffer tank between the precursor tank and the processing chamber. The at least one buffer tank is coupled to the precursor tank via a first pipe and coupled to the processing chamber via a second pipe.

A semiconductor structure is provided. The semiconductor structure includes an epitaxial structure over a semiconductor substrate. The semiconductor structure also includes a conductive feature over the semiconductor substrate. The conductive feature includes a high-k dielectric layer and a metal layer on the high-k dielectric layer, and a top surface of the metal layer is below a top surface of the high-k dielectric layer. The semiconductor structure further includes a metal-semiconductor compound layer formed on the epitaxial structure. In addition, the semiconductor structure includes a first metal contact structure formed on the top surface of the metal layer of the conductive feature. The semiconductor structure further includes a second metal contact structure formed on the metal-semiconductor compound layer.

A method for fabricating a semiconductor device includes the steps of: forming a fin-shaped structure on a substrate, forming a gate material layer on the fin-shaped structure, performing an etching process to pattern the gate material layer for forming a gate structure and a silicon residue, performing an ashing process on the silicon residue, and then performing a cleaning process to transform the silicon residue into a polymer stop layer on a top surface and sidewalls of the fin-shaped structure.

There is provided a technique that includes forming a film containing a first element and oxygen on a substrate by performing a cycle a predetermined number of times, the cycle including: (a) supplying a modifying agent to the substrate to form, on the substrate, an adsorption layer containing the modifying agent physically adsorbed on a surface of the substrate; (b) supplying a precursor containing the first element to the substrate and causing the precursor to react with the surface of the substrate to form a first layer containing the first element on the substrate; and (c) supplying an oxidizing agent to the substrate and causing the oxidizing agent to react with the first layer to modify the first layer into a second layer containing the first element and oxygen.

A method for treating a substrate includes arranging a substrate in a processing chamber. At least one of a vaporized solvent and a gas mixture including the solvent is supplied to the processing chamber to form a conformal liquid layer of the solvent on exposed surfaces of the substrate. The at least one of the vaporized solvent and the gas mixture is removed from the processing chamber. A reactive gas including a halogen species is supplied to the processing chamber. The conformal liquid layer adsorbs the reactive gas to form a reactive liquid layer that etches the exposed surfaces of the substrate.

A method for forming a foreign oxide or foreign nitride layer (6) on a substrate (1) of a semiconductor comprises providing a semiconductor substrate (1) having an oxidized or nitridized surface layer (3), supplying a foreign element (5) on the oxidized or nitridized surface layer; and keeping the oxidized or nitridized surface layer (3) at an elevated temperature so as to oxidize or nitridize at least partially the foreign element by the oxygen or nitrogen, respectively, initially present in the oxidized or nitridized surface layer (3).

The present disclosure provides a semiconductor device structure with a conductive contact and a method for preparing the semiconductor device structure. The semiconductor device structure includes a dielectric layer disposed over a semiconductor substrate; a conductive contact penetrating through the dielectric layer; and a metal oxide layer separating the conductive contact from the dielectric layer, wherein the conductive contact and the metal oxide layer comprise a same metal.

A method for treating a substrate includes arranging a substrate in a processing chamber. At least one of a vaporized solvent and a gas mixture including the solvent is supplied to the processing chamber to form a conformal liquid layer of the solvent on exposed surfaces of the substrate. The at least one of the vaporized solvent and the gas mixture is removed from the processing chamber. A reactive gas including a halogen species is supplied to the processing chamber. The conformal liquid layer adsorbs the reactive gas to form a reactive liquid layer that etches the exposed surfaces of the substrate.

Methods of forming a slurry and methods of performing a chemical mechanical polishing (CMP) process utilized in manufacturing semiconductor devices, as described herein, may be performed on semiconductor devices including integrated contact structures with ruthenium (Ru) plug contacts down to a semiconductor substrate. The slurry may be formed by mixing a first abrasive, a second abrasive, and a reactant with a solvent. The first abrasive may include a first particulate including titanium dioxide (TiO.sub.2) particles and the second abrasive may include a second particulate that is different from the first particulate. The slurry may be used in a CMP process for removing ruthenium (Ru) materials and dielectric materials from a surface of a workpiece resulting in better WiD loading and planarization of the surface for a flat profile.