Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing a barrier layer along a top surface of the semiconductor interconnect device; depositing and annealing a metal interconnect material over a top surface of the barrier layer, wherein the metal interconnect material fills the set of trenches and the set of vias; planarizing a top surface of the intermediate semiconductor interconnect device; exposing a portion of the barrier layer between the set of trenches and the set of vias; and depositing a dielectric cap. Also disclosed is an intermediate device formed by the method.

An aliphatic polycarbonate, an oxide precursor, and an oxide layer are provided, which are capable of controlling stringiness, when a thin film that can be employed for an electronic device or a semiconductor element is formed by a printing method. In an oxide precursor of the present invention, a compound of metal to be oxidized into a metal oxide is dispersed in a solution containing a binder (possibly including inevitable impurities) made of aliphatic polycarbonates, and an aliphatic polycarbonate having a molecular weight of 6000 or more and 400000 or less constitutes 80% by mass or more of all the aliphatic polycarbonates.

A method includes etching a dielectric layer to form a trench in the dielectric layer, depositing a metal layer extending into the trench, performing a nitridation process on the metal layer to convert a portion of the metal layer into a metal nitride layer, performing an oxidation process on the metal nitride layer to form a metal oxynitride layer, removing the metal oxynitride layer, and filling a metallic material into the trench using a bottom-up deposition process to form a contact plug.

A method for fabricating a metal oxide thin film transistor comprises selecting a substrate and fabricating a gate electrode thereon; growing a layer of dielectric or high permittivity dielectric on the substrate to serve as a gate dielectric layer; growing a first metal layer on the gate dielectric layer and a second metal layer on the first metal layer; fabricating a channel region at a middle position of the first metal layer and a passivation region at a middle position of the second metal layer; anodizing the metals of the passivation region and the channel region at atmospheric pressure and room temperature; fabricating a source and a drain; forming an active region comprising the source, the drain, and the channel region; depositing a silicon nitride layer on the active region; fabricating two electrode contact holes; depositing a metal aluminum film; and fabricating two metal contact electrodes by photolithography and etching.

A semiconductor structure includes first metal lines located above at least one semiconductor device, and a continuous metal organic framework (MOF) material layer including lower MOF portions that are located between neighboring pairs of first metal lines and an upper MOF matrix portion that continuously extends over the first metal lines and connected to each of the lower MOF portions.

Degradation of reliability of a semiconductor device is prevented. An electrode pad included mainly of aluminum is formed over a main surface of a semiconductor wafer. Subsequently, a first insulating member and a second insulating member are formed over the main surface of the semiconductor wafer so as to cover the electrode pad, and thereafter an opening portion that exposes a surface of the electrode pad is formed in the first insulating member and the second insulating member by a dry etching method using an etching gas including a halogen-based gas. Thereafter, an oxide film with a thickness of 2 nm to 6 nm is formed over the exposed surface of the electrode pad by performing a heat treatment at 200° C. to 300° C. in an air atmosphere, and then the semiconductor wafer is stored.

A trenched power semiconductor element, a trenched-gate structure thereof being in an element trench of an epitaxial layer and including at least a shielding electrode, a shielding dielectric layer, a gate electrode, an insulating separation layer, and a gate insulating layer. The shielding electrode is disposed at the bottom of the element trench, the shielding dielectric layer is disposed at a lower portion of the element trench, surrounding the shielding electrode to separate the shielding electrode from the epitaxial layer, wherein the top portion of the shielding dielectric layer includes a hole. The gate electrode is disposed above the shielding electrode, being separated from the hole at a predetermined distance through the insulating separation layer. The insulating separation layer is disposed between the shielding dielectric layer and the gate electrode layer to seal the hole.

A component such as a display may have a substrate and thin-film circuitry on the substrate. The thin-film circuitry may be used to form an array of pixels for a display or other circuit structures. Metal traces may be formed among dielectric layers in the thin-film circuitry. Metal traces may be provided with insulating protective sidewall structures. The protective sidewall structures may be formed by treating exposed edge surfaces of the metal traces. A metal trace may have multiple layers such as a core metal layer sandwiched between barrier metal layers. The core metal layer may be formed from a metal that is subject to corrosion. The protective sidewall structures may help prevent corrosion in the core metal layer. Surface treatments such as oxidation, nitridation, and other processes may be used in forming the protective sidewall structures.

A gallium nitride based semiconductor device is provided, where when a thickness of a transition layer is defined as the followings, the thickness of the transition layer is less than 1.5 nm: (i) a distance between a depth position at which an atomic composition of nitrogen element constituting the gallium nitride based semiconductor layer is ½ relative to that at a position on the GaN based semiconductor layer side sufficiently away from the transition layer, and a depth position at which an atomic composition of a metal element is ½ of a value of a maximum if an atomic composition of the metal element constituting an insulating layer has the maximum, or a depth position at which an atomic composition of the metal element is ½ relative to that at a position on the insulating layer side sufficiently away from the transition layer if not having the maximum.

A method of manufacturing a semiconductor device uses a semiconductor manufacturing apparatus including a turn table allowing placement of at least first and second semiconductor substrates and being capable of moving positions of the first and the second semiconductor substrates by turning, a first film forming chamber, and a second film forming chamber. The first and the second film forming chambers are provided with an opening capable of loading and unloading the first and the second semiconductor substrates by lifting and lowering the first and the second semiconductor substrates placed on the turn table. The method includes transferring the first and the second semiconductor substrates between the first and the second film forming chambers by turning the turn fable and lifting and lowering the first and the second semiconductor substrates placed on the turn table; and forming a stack of films above the first and the second semiconductor substrates.