Processing methods disclosed herein comprise forming a nucleation layer and a flowable chemical vapor deposition (FCVD) film on a substrate surface by exposing the substrate surface to a silicon-containing precursor and a reactant. By controlling at least one of a precursor/reactant pressure ratio, a precursor/reactant flow ratio and substrate temperature formation of miniature defects is minimized. Controlling at least one of the process parameters may reduce the number of miniature defects. The FCVD film can be cured by any suitable curing process to form a smooth FCVD film.

Embodiments of a three-dimensional (3D) memory device with a corrosion-resistant composite spacer and method for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack including a plurality of dielectric/sacrificial layer pairs is formed on a substrate. A memory string extending vertically through the dielectric stack is formed. A slit extending vertically through the dielectric stack is formed. A memory stack is formed on the substrate including a plurality of conductor/dielectric layer pairs by replacing, with a plurality of conductor layers, the sacrificial layers in the dielectric/sacrificial layer pairs through the slit. A composite spacer is formed along a sidewall of the slit. The composite spacer includes a first silicon oxide film, a second silicon oxide film, and a dielectric film formed laterally between the first silicon oxide film and the second silicon oxide film. A slit contact extending vertically in the slit is formed.

A method includes forming a film on a substrate by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: (a) forming a first layer by supplying a precursor to the substrate; and (b) forming a second layer by supplying a reactant to the substrate and modifying the first layer. The (a) includes: (a-1) supplying the precursor to the substrate from a first supply part while supplying an inert gas at a first flow rate, and supplying an inert gas at a second flow rate from a second supply part; and (a-2) supplying the precursor to the substrate while supplying the inert gas at a third flow rate from the first supply part, or supplying the precursor from the first supply part while stopping the supply of the inert gas, and supplying the inert gas at a fourth flow rate from the second supply part.

A method of preparing a self-aligned via on a semiconductor workpiece includes using an integrated sequence of processing steps executed on a common manufacturing platform hosting a plurality of processing modules including one or more film-forming modules, one or more etching modules, and one or more transfer modules. The integrated sequence of processing steps include receiving the workpiece into the common manufacturing platform, the workpiece having a pattern of metal features in a dielectric layer wherein exposed surfaces of the metal features and exposed surfaces of the dielectric layer together define an upper planar surface; selectively etching the metal features to form a recess pattern by recessing the exposed surfaces of the metal features beneath the exposed surfaces of the dielectric layer using one of the one or more etching modules; and depositing an etch stop layer over the recess pattern using one of the one or more film-forming modules.

A SiC film structure for obtaining a three-dimensional SiC film by forming the SiC film in an outer circumference of a substrate using a vapor deposition type film formation method and removing the substrate, the SiC film structure including: a main body having a three-dimensional shape formed of a SiC film and having an opening for removing the substrate; a lid configured to cover the opening; and a SiC coat layer configured to cover at least a contact portion between the main body and an outer edge portion of the lid and join the main body and the lid.

A semiconductor device includes a substrate, a semiconductor stacking portion formed on the substrate, a silicon nitride passivation film covering the surface of the semiconductor stacking portion, and oxygen atoms existing at an interface between the silicon nitride passivation film and the semiconductor stacking portion. The semiconductor stacking portion includes a plurality of nitride semiconductor layers. The interfacial oxygen content at the passivation film and stacking portion interface is 0.6×10.sup.15 oxygen atoms/cm.sup.2 or less.

In a method of manufacturing a semiconductor device, a gate structure is formed over a fin structure. A source/drain region of the fin structure is recessed. A first semiconductor layer is formed over the recessed source/drain region. A second semiconductor layer is formed over the first semiconductor layer. The fin structure is made of Si.sub.xGe.sub.1-x, where 0≤x≤0.3, the first semiconductor layer is made of Si.sub.yGe.sub.1-y, where 0.45≤y≤1.0, and the second semiconductor layer is made of Si.sub.zGe.sub.1-z, where 0≤z≤0.3.

A method includes forming a silicon liner over a semiconductor device, which includes a dummy gate structure disposed over a substrate and S/D features disposed adjacent to the dummy gate structure, where the dummy gate structure traverses a channel region between the S/D features. The method further includes forming an ILD layer over the silicon liner, which includes elemental silicon, introducing a dopant species to the ILD layer, and subsequently removing the dummy gate structure to form a gate trench. Thereafter, the method proceeds to performing a thermal treatment to the doped ILD layer, thereby oxidizing the silicon liner, and forming a metal gate stack in the gate trench and over the oxidized silicon liner.

A method for manufacturing a semiconductor feature includes: alternatingly forming first and second dielectric layers on a semiconductor substrate along a vertical direction; forming multiple spaced-apart trenches penetrating the first and second dielectric layers; forming multiple support segments filling the trenches; removing the second dielectric layers to form multiple spaces; forming multiple conductive layers filling the spaces; removing the support segments to expose the conductive layers and the first dielectric layers; selectively forming a blocking layer covering the first dielectric layers outside of the conductive layers; forming multiple selectively-deposited sub-layers on the exposed conductive layers outside of the blocking layer and each connected to one of the conductive layers; forming multiple channel sub-layers on the selectively-deposited sub-layers outside of the blocking layer; removing the blocking layer; forming multiple isolation sub-layers filling the trenches; and forming multiple source/drain segments each connected to corresponding ones of the channel sub-layers.

A semiconductor device and fabrication method thereof are provided. The fabrication method include: providing a to-be-etched material layer; forming a plurality of discrete sacrificial layers on the to-be-etched material layer; forming first initial spacers on sidewalls of each of the discrete sacrificial layers. Each first initial spacer includes a first bottom region and a first top region on the first bottom region; removing the discrete sacrificial layers. The method further includes: removing the first top region of each first initial spacer to form a first spacer from each first bottom region; forming second spacers on sidewalls of each of the first spacers. Each second spacer includes a second bottom region and a second top region on the second bottom region; removing the first spacers; The method further includes: removing the second top regions by etching; and etching the to-be-etched material layer by using the second spacers as a mask.