Patent classifications
H01L21/02315
Cyclic low temperature film growth processes
A method of nitridation includes cyclically performing the following steps in situ within a processing chamber at a temperature less than about 400° C.: treating an unreactive surface of a substrate in the processing chamber to convert the unreactive surface to a reactive surface by exposing the unreactive surface to an energy flux, and nitridating the reactive surface using a nitrogen-based gas to convert the reactive surface to a nitride layer including a subsequent unreactive surface.
Cyclic Low Temperature Film Growth Processes
A method of nitridation includes cyclically performing the following steps in situ within a processing chamber at a temperature less than about 400° C.: directing an energy flux to a localized region of an unreactive surface of a substrate to convert the localized region of the unreactive surface to a localized reactive region: and selectively nitridating the localized reactive region using a nitrogen-based gas to convert the localized reactive region to a nitride layer.
CVD BASED OXIDE-METAL MULTI STRUCTURE FOR 3D NAND MEMORY DEVICES
Implementations described herein generally relate to a method for forming a metal layer and to a method for forming an oxide layer on the metal layer. In one implementation, the metal layer is formed on a seed layer, and the seed layer helps the metal in the metal layer nucleate with small grain size without affecting the conductivity of the metal layer. The metal layer may be formed using plasma enhanced chemical vapor deposition (PECVD) and nitrogen gas may be flowed into the processing chamber along with the precursor gases. In another implementation, a barrier layer is formed on the metal layer in order to prevent the metal layer from being oxidized during subsequent oxide layer deposition process. In another implementation, the metal layer is treated prior to the deposition of the oxide layer in order to prevent the metal layer from being oxidized.
ATOMIC LAYER DEPOSITION METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE
A method for manufacturing semiconductor structure is disclosed. The method includes: providing a semiconductor substrate; hydrogenizing a surface of the semiconductor substrate; supplying a precursor to the surface of the semiconductor substrate; and supplying a reactant to the surface of the semiconductor substrate. An associated method for performing an atomic layer deposition (ALD) upon a semiconductor substrate and an associated atomic layer deposition (ALD) method are also disclosed.
Treatment for flowable dielectric deposition on substrate surfaces
Provided herein are methods and apparatus for improved flowable dielectric deposition on substrate surfaces. The methods involve improving nucleation and wetting on the substrate surface without forming a thick high wet etch rate interface layer. According to various embodiments, the methods may include single or multi-stage remote plasma treatments of a deposition surface. In some embodiments, a treatment may include exposure to both a reducing chemistry and a hydrogen-containing oxidizing chemistry. Apparatus for performing the methods are also provided.
Methods For Depositing Blocking Layers On Metal Surfaces
Methods of enhancing selective deposition are described. In some embodiments, a blocking layer is deposited on a metal surface before deposition of a dielectric. In some embodiments, a metal surface is functionalized to enhance or decrease its reactivity.
SELECTIVE TANTALUM NITRIDE DEPOSITION FOR BARRIER APPLICATIONS
Methods of forming semiconductor devices by enhancing selective deposition are described. In some embodiments, a blocking layer is deposited on a metal surface before deposition of a barrier layer. A substrate with a metal surface, a dielectric surface and an aluminum oxide surface has a blocking layer deposited on the metal surface using an alkylsilane.
DEPOSITION OF SILICON NITRIDE WITH ENHANCED SELECTIVITY
The use of selective deposition of silicon nitride can eliminate conventional patterning steps by allowing silicon nitride to be deposited only in selected and desired areas. Using a silicon iodide precursor alternately with a thermal nitrogen source in an ALD or pulsed CVD mode, silicon nitride can be deposited preferentially on a surface such as silicon nitride, silicon dioxide, germanium oxide, SiCO, SiOF, silicon carbide, silicon oxynitride, and low k substrates, while exhibiting very little deposition on exposed surfaces such as titanium nitride, tantalum nitride, aluminum nitride, hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, tantalum oxide, niobium oxide, lanthanum oxide, yttrium oxide, magnesium oxide, calcium oxide, and strontium oxide.
Semiconductor Devices and Methods of Manufacture
Semiconductor devices and methods of manufacturing the semiconductor devices are described herein. A method includes forming a first opening through a dielectric layer, the opening exposing a conductive region. A wet cleaning is used after the forming the first opening, and the first opening is treated after the wet cleaning the first opening, the treating the first opening comprising turning a sidewall treatment precursor and a bottom treatment precursor into a first plasma mixture, the sidewall treatment precursor being different from the bottom treatment precursor. The first opening is filled with a conductive material after the treating the first opening.
Multi-channel devices and methods of manufacture
The disclosure is directed towards semiconductor devices and methods of manufacturing the semiconductor devices. The methods include forming fins in a device region and forming other fins in a multilayer stack of semiconductor materials in a multi-channel device region. A topmost nanostructure may be exposed in the multi-channel device region by removing a sacrificial layer from the top of the multilayer stack. Once removed, a stack of nanostructures are formed from the multilayer stack. A native oxide layer is formed to a first thickness over the topmost nanostructure and to a second thickness over the remaining nanostructures of the stack, the first thickness being greater than the second thickness. A gate dielectric is formed over the fins in the device region. A gate electrode is formed over the gate dielectric in the device region and surrounding the native oxide layer in the multi-channel device region.