H01L21/0234

Substrate processing method

A substrate processing method capable of achieving uniform etch selectivity in the entire thickness range of a thin film formed on a stepped structure includes: forming a thin film on a substrate by performing a plurality of cycles including forming at least one layer and applying plasma to the at least one layer under a first process condition; and applying plasma to the thin film under a second process condition different from the first process condition.

Structures including multiple carbon layers and methods of forming and using same

Methods and systems for forming a structure including multiple carbon layers and structures formed using the method or system are disclosed. Exemplary methods include forming a first carbon layer and a second carbon layer, wherein a density and/or other property of the first carbon layer differs from the corresponding property of the second carbon layer.

Semiconductor device and method for manufacturing the same

A semiconductor device includes a bottom electrode, a top electrode, a sidewall spacer, and a data storage element. The sidewall spacer is disposed aside the top electrode. The data storage element is located between the bottom electrode and the top electrode, and includes a ferroelectric material. The data storage element has a peripheral region which is disposed beneath the sidewall spacer and which has at least 60% of ferroelectric phase. A method for manufacturing the semiconductor device and a method for transforming a non-ferroelectric phase of a ferroelectric material to a ferroelectric phase are also disclosed.

SOFT ASHING PROCESS FOR FORMING PROTECTIVE LAYER ON CONDUCTIVE CAP LAYER OF SEMICONDUCTOR DEVICE

A method for making a semiconductor device includes patterning at least one dielectric layer disposed over a conductive cap layer to form a via opening penetrating through the at least one dielectric layer to expose the conductive cap layer and to form a top portion of the conductive cap layer into a metal oxide layer; converting the metal oxide layer to a metal oxynitride layer by a soft ashing process using a processing gas containing nitrogen gas; removing the metal oxynitride layer from a remaining portion of the conductive cap layer; and forming a via contact in the via opening to electrically connect the remaining portion of the conductive cap layer.

INERT GAS IMPLANTATION FOR HARD MASK SELECTIVITY IMPROVEMENT

An amorphous carbon hard mask is formed having low hydrogen content and low sp3 carbon bonding but high modulus and hardness. The amorphous carbon hard mask is formed by depositing an amorphous carbon layer at a low temperature in a plasma deposition chamber and treating the amorphous carbon layer to a dual plasma-thermal treatment. The dual plasma-thermal treatment includes exposing the amorphous carbon layer to inert gas plasma for implanting an inert gas species in the amorphous carbon layer and exposing the amorphous carbon layer to a high temperature. The amorphous carbon hard mask has high etch selectivity relative to underlying materials.

METHOD OF LINEARIZED FILM OXIDATION GROWTH

Methods of forming an oxide layer over a semiconductor substrate are provided. The method includes forming a first oxide containing portion of the oxide layer over a semiconductor substrate at a first growth rate by exposing the substrate to a first gas mixture having a first oxygen percentage at a first temperature. A second oxide containing portion is formed over the substrate at a second growth rate by exposing the substrate to a second gas mixture having a second oxygen percentage at a second temperature. A third oxide containing portion is formed over the substrate at a third growth rate by exposing the substrate to a third gas mixture having a third oxygen percentage at a third temperature. The first growth rate is slower than each subsequent growth rate and each growth rate subsequent to the second growth rate is within 50% of each other.

HIGH BREAKDOWN VOLTAGE ETCH-STOP LAYER

The present disclosure relates to a method of forming a semiconductor structure. The method includes depositing an etch-stop layer (ESL) over a first dielectric layer. The ESL layer deposition can include: flowing a first precursor over the first dielectric layer; purging at least a portion of the first precursor; flowing a second precursor over the first dielectric layer to form a sublayer of the ESL layer; and purging at least a portion of the second precursor. The method can further include depositing a second dielectric layer on the ESL layer and forming a via in the second dielectric layer and through the ESL layer.

GATE STRUCTURES IN TRANSISTOR DEVICES AND METHODS OF FORMING SAME

A semiconductor device includes first transistor having a first gate stack and first source/drain regions on opposing sides of the first gate stack; a second transistor having a second gate stack and second source/drain regions on opposing sides of the second gate stack; and a gate isolation structure separating the first gate stack from the second gate stack. The gate isolation structure includes a dielectric liner having a varied thickness along sidewalls of the first gate stack and the second gate stack and a dielectric fill material over the dielectric liner, wherein the dielectric fill material comprises a seam.

Methods of forming hardmasks

Embodiments of the present disclosure generally relate to methods of forming hardmasks. Embodiments described herein enable, e.g., formation of carbon-containing hardmasks having reduced film stress. In an embodiment, a method of processing a substrate is provided. The method includes positioning a substrate in a processing volume of a processing chamber and depositing a diamond-like carbon (DLC) layer on the substrate. After depositing the DLC layer, the film stress is reduced by performing a plasma treatment, wherein the plasma treatment comprises applying a radio frequency (RF) bias power of about 100 W to about 10,000 W.

DIELECTRIC STRUCTURES IN SEMICONDUCTOR DEVICES

A semiconductor device with densified dielectric structures and a method of fabricating the same are disclosed. The method includes forming a fin structure, forming an isolation structure adjacent to the fin structure, forming a source/drain (S/D) region on the fin structure, depositing a flowable dielectric layer on the isolation structure, converting the flowable dielectric layer into a non-flowable dielectric layer, performing a densification process on the non-flowable dielectric layer, and repeating the depositing, converting, and performing to form a stack of densified dielectric layers surrounding the S/D region.