Embodiments of the disclosure include methods of forming a film comprising conformally depositing a first film on a substrate; treating the first film with a first plasma to form a second film; treating the second film with a second plasma to form a third film; and selectively removing the first film, a portion of the second film, and the third film.

The present disclosure is directed to method for the fabrication of spacer structures between source/drain (S/D) epitaxial structures and metal gate structures in nanostructure transistors. The method includes forming a fin structure with alternating first and second nanostructure elements on a substrate. The method also includes etching edge portions of the first nanostructure elements in the fin structure to form cavities. Further, depositing a spacer material on the fin structure to fill the cavities and removing a portion of the spacer material in the cavities to form an opening in the spacer material. In addition, the method includes forming S/D epitaxial structures on the substrate to abut the fin structure and the spacer material so that sidewall portions of the S/D epitaxial structures seal the opening in the spacer material to form an air gap in the spacer material.

A semiconductor structure includes a first dielectric layer, a first conductive feature, a second conductive feature, a first etch stop layer, and a conductive via. The first conductive feature and the second conductive feature are embedded in the first dielectric layer. The first etch stop layer is disposed over the dielectric layer. The conductive via is surrounded by the first etch stop layer and electrically connected to the first conductive feature, in which the conductive via is in contact with a top surface of the first etch stop layer.

A device includes a semiconductor substrate, a fin structure on the semiconductor substrate, a gate structure on the fin structure, and a pair of source/drain features on both sides of the gate structure. The gate structure includes an interfacial layer on the fin structure, a gate dielectric layer on the interfacial layer, and a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer. The gate dielectric layer includes nitrogen element.

A method for manufacturing a semiconductor device includes forming contacts disposed in a dielectric layer. The method of forming the contacts includes forming contact holes and then filling with a conductive material. The method of forming the contact holes includes steps of forming openings in the dielectric layer to expose active regions, introducing a first oxygen plasma and a first fluorine plasma to remove by-products and oxidize inner surfaces of the openings, introducing a second oxygen plasma and a second fluorine plasma to remove the oxidized inner surfaces and repair the active regions, introducing a third oxygen plasma to oxidize inner surfaces again to form an oxide layer, and removing the oxide layer. The cross-sectional structure of two adjacent contact holes includes a capital, a base, and a shaft between the capital and the base, wherein the shaft has a smaller width than the base and the capital.

A semiconductor memory device includes a gate stack structure and a plurality of channel structures. The gate stack structure includes an insulating interlayer and a gate conductive layer that are alternately stacked. The plurality of channel holes is formed in the gate stack structure. The plurality of channel holes includes a fluorine-containing layer, a first blocking layer, and a charge-trapping layer. The fluorine-containing layer is formed on surfaces of the channel holes for forming the plurality of channel structures. The first blocking layer is formed on the fluorine-containing layer along the surfaces of the channel holes. The charge-trapping layer is formed on the first blocking layer along the surfaces of the channel holes.

A method comprises forming a gate structure over a semiconductor substrate; forming an etch stop layer over the gate structure and an ILD layer over the etch stop layer; performing a first etching process to form a gate contact opening extending through the ILD layer into the etch stop layer, resulting in a sidewall of the etch stop layer being exposed in the gate contact opening; oxidizing the exposed sidewall of the etch stop layer; after oxidizing the exposed sidewall of the etch stop layer, performing a second etching process to deepen the gate contact opening; and forming a gate contact in the deepened gate contact opening.

Embodiments include nanostructure devices and methods of forming nanostructure devices which include a treatment process to expand a sidewall spacer material to close a seam in the sidewall spacer material after deposition. The treatment process includes oxygen plasma treatment to expand the sidewall spacer material and crosslink the open seam to form a closed seam, lower k-value, and decrease density.

Semiconductor devices and methods of manufacturing are presented in which a first spacer layer and a second spacer layer are formed. In embodiments the first spacer layer and the second spacer layer are formed with an enhanced etch resistance. Such an enhanced etch resistance works to help prevent undesired breakthroughs during subsequent manufacturing processes.

A semiconductor device with a small variation in transistor characteristics is provided. The semiconductor device includes an oxide semiconductor film, a source electrode and a drain electrode over the oxide semiconductor film, an interlayer insulating film placed to cover the oxide semiconductor film, the source electrode, and the drain electrode, a first gate insulating film over the oxide semiconductor film, a second gate insulating film over the first gate insulating film, and a gate electrode over the second gate insulating film. The interlayer insulating film has an opening overlapping with a region between the source electrode and the drain electrode, the first gate insulating film, the second gate insulating film, and the gate electrode are placed in the opening of the interlayer insulating film, the first gate insulating film includes oxygen and aluminum, and the first gate insulating film includes a region thinner that is than the second gate insulating film.