A method is presented for forming a fully aligned via (FAV) structure. The method includes depositing a first dielectric adjacent a conductive material, forming a surface aligned monolayer (SAM) over the conductive material, the SAM defining a long chain SAM formed by a layer-by-layer growth technique, depositing a second dielectric over the SAM and the first dielectric, performing chemical mechanical polishing (CMP) to planarize the second dielectric, and etching the SAM to form the FAV structure.

An integrated circuit device includes a substrate having a first portion in a first device region and a second portion in a second device region. A first semiconductor strip is in the first device region. A dielectric liner has an edge contacting a sidewall of the first semiconductor strip, wherein the dielectric liner is configured to apply a compressive stress or a tensile stress to the first semiconductor strip. A Shallow Trench Isolation (STI) region is over the dielectric liner, wherein a sidewall and a bottom surface of the STI region is in contact with a sidewall and a top surface of the dielectric liner.

A substrate processing method according to an embodiment includes a processing liquid supply step and an UV irradiation step. In the processing liquid supply step, a processing liquid is supplied to a substrate. In the UV irradiation step, the substrate after the processing liquid supply step is irradiated with ultraviolet rays having a wavelength of 200 nm or less, so that the substrate after the processing liquid supply step is destaticized.

A substrate is positioned in exposure to a plasma generation region within a plasma processing chamber. A first plasma is generated within the plasma generation region. The first plasma is configured to cause deposition of a film on the substrate until the film deposited on the substrate reaches a threshold film thickness. The substrate is then exposed to ultraviolet radiation to resolve defects within the film deposited on the substrate. The ultraviolet radiation can be supplied in-situ using either a second plasma configured to generate ultraviolet radiation or an ultraviolet irradiation device disposed in exposure to the plasma generation region. The ultraviolet radiation can also be supplied ex-situ by moving the substrate to an ultraviolet irradiation device separate from the plasma processing chamber. The substrate can be exposed to the ultraviolet radiation in a repeated manner to resolve defects within the deposited film as the film thickness increases.

A semiconductor device and method of manufacture comprise forming a channel-less, porous low K material. The material may be formed using a silicon backbone precursor and a hydrocarbon precursor to form a matrix material. The material may then be cured to remove a porogen and help to collapse channels within the material. As such, the material may be formed with a scaling factor of less than or equal to about 1.8.

Generally, examples are provided relating to filling gaps with a dielectric material, such as filling trenches between fins for Shallow Trench Isolations (STIs). In an embodiment, a first dielectric material is conformally deposited in a trench using an atomic layer deposition (ALD) process. After conformally depositing the first dielectric material, the first dielectric material is converted to a second dielectric material. In further examples, the first dielectric material can be conformally deposited in another trench, and a fill dielectric material can be flowed into the other trench and converted.

Embodiments described herein provide a method of forming a silicon-and-oxygen-containing layer having covalent Si—O—Si bonds by cross-linking terminal silanol groups. The method includes positioning a substrate in a chamber. The substrate has one or more trenches including a width of 10 nanometers (nm) or less, and an aspect ratio of 2:1 or greater. The aspect ratio is defined by a ratio of a depth to the width of the one or more trenches. A silicon-and-oxygen-containing layer is disposed over the one or more trenches. The silicon-and-oxygen-containing layer has terminal silanol groups. The substrate is heated, and the silicon-and-oxygen-containing layer is exposed to an ammonia or amine group-containing precursor distributed across a process volume.

A compound semiconductor device includes a compound semiconductor stack structure, a protective film provided on the compound semiconductor stack structure and containing titanium oxide, and a polycrystalline diamond film provided on the protective film.

Methods and systems for forming a structure including a dielectric material layer on a surface of a substrate and structures and devices formed using the method or system are disclosed. Exemplary methods include providing a substrate within a reaction chamber of a reactor system, providing one or more precursors to the reaction chamber, and providing pulsed plasma power to polymerize the one or more precursors within the reaction chamber.

A semiconductor device and a method of forming a semiconductor device include forming a dielectric material, performing a wet oxidation treatment on the dielectric material, and performing a dry anneal on the dielectric material. The dielectric material may be a flowable material. The wet oxidation treatment may include an acid and oxidizer mixture.