Methods and systems for forming a cured low-k material layer on a surface of a substrate and structures and devices formed using the method or system are disclosed. Exemplary methods include providing a substrate within a reaction chamber of a reactor system, providing one or more precursors to the reaction chamber, providing plasma power to polymerize the one or more precursors, and curing the low-k material with activated species to form the cured low-k material layer.

An integrated circuit device includes a substrate having a first portion in a first device region and a second portion in a second device region. A first semiconductor strip is in the first device region. A dielectric liner has an edge contacting a sidewall of the first semiconductor strip, wherein the dielectric liner is configured to apply a compressive stress or a tensile stress to the first semiconductor strip. A Shallow Trench Isolation (STI) region is over the dielectric liner, wherein a sidewall and a bottom surface of the STI region is in contact with a sidewall and a top surface of the dielectric liner.

There is provided a technique of forming an insulating film containing silicon oxide. A coating solution containing polysilazane is applied onto a wafer W, the solvent of the coating solution is volatilized, and the coating film is irradiated with ultraviolet rays in nitrogen atmosphere before performing a curing process. Dangling bonds are generated in silicon which is a pre-hydrolyzed site in polysilazane. Therefore, the energy for hydrolysis is reduced, and unhydrolyzed sites are reduced even when the temperature of the curing process is 350° C. Since efficient dehydration condensation occurs, the crosslinking rate is improved, and a dense (good-quality) insulation film is formed. By forming a protective film on the surface of the coating film to which ultraviolet rays irradiated, the reaction of dangling bonds prior to the curing process is suppressed.

A method of making a semiconductor device includes forming a gate stack on a substrate. The method further includes depositing a first spacer layer on a sidewall of the gate stack. The first spacer layer includes silicon and carbon. The method includes performing a first nitrogen plasma treatment process on the first spacer layer to increase a density of the first spacer layer. The method further includes depositing a second spacer layer on the first spacer layer. The second spacer layer includes silicon, carbon, and nitrogen.

An apparatus is provided. The apparatus has a chuck having a first side configured to retain a superstrate or a template and a second side, an array of image sensors disposed at the second side of the chuck and spaced from the chuck, and an array of light sources disposed between the transparent chuck and the array of image sensors.

A method for manufacturing a semiconductor device, includes: forming a shallow trench isolation structure surrounding a first semiconductor fin and a second semiconductor fin; forming a dummy gate structure across the first and second semiconductor fins; forming a first flowable dielectric layer over the first and second semiconductor fins; curing the first flowable dielectric layer at a first temperature; removing a first portion of the cured first flowable dielectric layer from above the second semiconductor fin; after removing the first portion of the cured first flowable dielectric layer, forming a second flowable dielectric layer over the second semiconductor fin; curing the second flowable dielectric layer at a second temperature different from the first temperature; and replacing the dummy gate structure with a metal gate structure.

A first layer is located over a substrate. The first layer includes a first dielectric component and a first conductive component. A first etching stop layer is located over the first dielectric component. A metal capping layer is located over the first conductive component. A second etching stop layer is located over the first etching stop layer and over the metal capping layer. A second layer is located over the second etching stop layer. The second layer includes a second dielectric component and a second conductive component. A third conductive component electrically interconnects the second conductive component to the first conductive component.

A semiconductor device and method of manufacture comprise forming a channel-less, porous low K material. The material may be formed using a silicon backbone precursor and a hydrocarbon precursor to form a matrix material. The material may then be cured to remove a porogen and help to collapse channels within the material. As such, the material may be formed with a scaling factor of less than or equal to about 1.8.

A method of deposition is disclosed. The method can include dispensing a formable material over a substrate, where the substrate includes a non-uniform surface topography, and where the substrate includes an active zone and an exclusion zone. The method can also include curing the formable material in the exclusion zone to form a circular edge between the exclusion zone and the active zone, contacting the formable material with a superstrate, and curing the formable material in the active zone to form a layer over the substrate, wherein curing is performed while the superstrate is contacting the formable material.

Plasma processing apparatus and associated methods are provided. In one example, a plasma processing apparatus includes a plasma chamber. The plasma processing apparatus includes a dielectric wall forming at least a portion of the plasma chamber. The plasma processing apparatus includes an inductive coupling element located proximate the dielectric wall. The plasma processing apparatus includes an ultraviolet light source configured to emit an ultraviolet light beam onto a metal surface that faces an interior volume of the plasma chamber. The plasma processing apparatus includes a controller configured to control the ultraviolet light source.