Patent classifications
H01L21/02348
Nano multilayer carbon-rich low-k spacer
A method of making a semiconductor device includes forming a gate stack on a substrate. The method further includes depositing a first spacer layer on a sidewall of the gate stack. The first spacer layer includes silicon and carbon. The method includes performing a first nitrogen plasma treatment process on the first spacer layer to increase a density of the first spacer layer. The method further includes depositing a second spacer layer on the first spacer layer. The second spacer layer includes silicon, carbon, and nitrogen.
Method and apparatus for manufacturing semiconductor device
The present disclosure provides a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device includes the following operations. An intermediate layer is formed in the semiconductor device. A field is applied to the intermediate layer, wherein the field source does not contact the semiconductor device. The polarity of the intermediate layer is changed by the field to form a desired dipole orientation in the intermediate layer.
Self-aligned internal spacer with EUV
A method of forming aligned gates for horizontal nanowires or nanosheets, comprising: providing a wafer which comprises at least one fin of sacrificial layers alternated with functional layers, and a dummy gate covering a section of the fin between a first end and a second end; at least partly removing the sacrificial layers at the first end and the second end thereby forming a void between the functional layers at the first and end such that the void is partly covered by the dummy gate; providing resist material which oxidizes upon EUV exposure; exposing the wafer to EUV light; selectively removing the dummy gate and the unexposed resist; forming a gate between the functional layers and between the exposed resist at the first end and at the second end.
METHOD OF FORMING INSULATING LAYER
A method of forming an insulating layer on a first interconnect layer formed on a first surface of a wafer includes a step of coating an upper surface of the first interconnect layer and the upper surface of the wafer with a thermosetting resin, a step of modifying predetermined regions of the thermosetting resin into modified resin portions, a step of dissolving the modified resin portions modified in the modifying step with a chemical solution and thereafter removing the dissolved modified resin portions by supplying a cleaning fluid to the wafer, a step of accommodating the wafer into a hermetically sealable chamber, hermetically sealing the chamber, and making the chamber free of oxygen, and a step of heating the wafer accommodated in the chamber that has been made free of oxygen to thermoset the thermosetting resin.
METHODS FOR MAKING EUV PATTERNABLE HARD MASKS
Methods for making thin-films on semiconductor substrates, which may be patterned using EUV, include: mixing a vapor stream of an organometallic precursor with a vapor stream of a counter-reactant so as to form a polymerized organometallic material; and depositing the organometallic polymer-like material onto the surface of the semiconductor substrate. The mixing and depositing operations may be performed by chemical vapor deposition (CVD), atomic layer deposition (ALD), and ALD with a CVD component, such as a discontinuous, ALD-like process in which metal precursors and counter-reactants are separated in either time or space.
Dielectric plugs
A method according to some embodiments of the present disclosure includes providing a workpiece that include an opening and a top surface, depositing a dielectric material over the workpiece and into the opening to form a first dielectric layer that has a top portion over the top surface and a plug portion in the opening, treating the first dielectric layer to convert top portion into a second dielectric layer different from the first dielectric layer, and selectively removing the second dielectric layer.
Plasma processing apparatus and plasma processing method
A plasma processing apparatus includes: a processing chamber in which a sample is subjected to plasma treatment; a radio frequency power supply configured to supply radio frequency power that generates plasma; a sample stage on which the sample is placed; and an ultraviolet light source configured to apply an ultraviolet ray. The apparatus further includes a controller configured to control the ultraviolet light source such that before the radio frequency power is supplied into the processing chamber, a pulse-modulated ultraviolet ray is applied into the processing chamber.
Method and apparatus for forming self-aligned via with selectively deposited etching stop layer
A first layer is located over a substrate. The first layer includes a first dielectric component and a first conductive component. A first etching stop layer is located over the first dielectric component. A metal capping layer is located over the first conductive component. A second etching stop layer is located over the first etching stop layer and over the metal capping layer. A second layer is located over the second etching stop layer. The second layer includes a second dielectric component and a second conductive component. A third conductive component electrically interconnects the second conductive component to the first conductive component.
BOTTOM-UP CURING OF DIELECTRIC FILMS IN INTEGRATED CIRCUITS
Embodiments of the invention include a method of forming a multi-layer integrated circuit (IC) structure that includes forming a passive energy source formed from a conductive metal. A dielectric target layer is formed over the first energy source. An active energy source is used to generate electromagnetic radiation having a predetermined wavelength, wherein the dielectric target layer is substantially transparent to the electromagnetic radiation at the predetermined wavelength. The dielectric target layer is exposed to the electromagnetic radiation by transmitting the electromagnetic radiation into and through the dielectric target layer to impact the passive energy source. The passive energy source is configured to, based at least in part on being exposed to the electromagnetic radiation, absorb the electromagnetic radiation, experience a conductive material temperature increase such that the conductive material generates heat energy, and emit the generated heat energy to the dielectric target layer.
REPASSIVATION APPLICATION FOR WAFER-LEVEL CHIP-SCALE PACKAGE
In described examples, a method of printing repassivation onto a substrate includes depositing an ink comprising particles of a repassivation material onto specified locations on a surface of the substrate using an inkjet printer, and curing the repassivation material. The ink is deposited so that specified portions of the substrate surface are not covered by the ink