The present disclosure generally relates to substrate processing methods, such as etching methods with noble gases at low temperatures. In an aspect, the method includes exposing a substrate, a first layer comprising a gas, and a fluorine-containing layer to energy to form a passivation layer while maintaining the substrate at conditions encompassing a triple point temperature of the gas, the substrate positioned in a processing region of a processing chamber. The method further includes etching the substrate with ions.

A method of post-treating a dielectric film formed on a surface of a substrate includes positioning a substrate having a dielectric film formed thereon in a processing chamber and exposing the dielectric film to microwave radiation in the processing chamber at a frequency between 5 GHz and 7 GHz.

A method for making a dense organosilicon film with improved mechanical properties, the method comprising the steps of: providing a substrate within a reaction chamber; introducing into the reaction chamber a gaseous composition comprising hydrido-dimethyl-alkoxysilane; and applying energy to the gaseous composition comprising hydrido-dimethyl-alkoxysilane in the reaction chamber to induce reaction of the gaseous composition comprising hydrido-dimethyl-alkoxysilane to deposit an organosilicon film on the substrate, wherein the organosilicon film has a dielectric constant from ˜2.70 to ˜3.50, an elastic modulus of from ˜6 to ˜36 GPa, and an at. % carbon from ˜10 to ˜36 as measured by XPS.

Method of forming low-k films with reduced dielectric constant, reduced CHx content, and increased hardness are described. A siloxane film is on a substrate surface using a siloxane precursor comprising O—Si—O bonds and cured using ultraviolet light.

Methods for seam-less gapfill comprising forming a flowable film by PECVD and curing the flowable film to solidify the film. The flowable film can be formed using a higher order silane and plasma. A UV cure, or other cure, can be used to solidify the flowable film.

A low-k dielectric porous silicon oxycarbon layer is formed within an integrated circuit. In one embodiment, a porogen and bulk layer containing silicon oxycarbon layer is deposited, the porogens are selectively removed from the formed layer without simultaneously cross-linking the bulk layer, and then the bulk layer material is cross-linked. In other embodiments, multiple silicon oxycarbon sublayers are deposited, porogens from each sub-layer are selectively removed without simultaneously cross-linking the bulk material of the sub-layer, and the sub-layers are cross-linked separately.

A semiconductor device includes an N-type fin-like field effect, a P-type fin-like field effect transistor, a shallow trench isolation (STI) structure, a first interlayer dielectric (ILD) layer, and a second ILD layer. The N-type fin-like field effect transistor includes a first semiconductor fin, a gate structure across the first semiconductor fin, and a first source/drain feature in contact with the first semiconductor fin. The P-type fin-like field effect transistor includes a second semiconductor fin, the gate structure across the second semiconductor fin, and a second source/drain feature in contact with the second semiconductor fin. The structure surrounds the first and second semiconductor fins. The first interlayer dielectric (ILD) layer covers the first source/drain feature. The second ILD layer covers the second source/drain feature, wherein a porosity of the second ILD layer is greater than a porosity of the first ILD layer.

Silicon oxide layer is deposited on a semiconductor substrate by PECVD at a temperature of less than about 200° C. and is treated with helium plasma to reduce stress of the deposited layer to an absolute value of less than about 80 MPa. Plasma treatment reduces hydrogen content in the silicon oxide layer, and leads to low stress films that can also have high density and low roughness. In some embodiments, the film is deposited on a semiconductor substrate that contains one or more temperature-sensitive layers, such as layers of organic material or spin-on dielectric that cannot withstand temperatures of greater than 250° C. In some embodiments the silicon oxide film is deposited to a thickness of between about 100-200 Å, and is used as a hardmask layer during etching of other layers on a semiconductor substrate.

A method for manufacturing a semiconductor device is provided, including forming a fin field effect transistor (FinFET) structure on a semiconductor substrate. The FinFET structure includes at least one fin, and a gate electrode structure and source/drain regions on the at least one fin. A dielectric film is formed over the at least on fin. The dielectric film is irradiated with ultra violet (UV) radiation from a single UV source.

In an embodiment, a device includes: a gate structure over a substrate; a gate spacer adjacent the gate structure; a source/drain region adjacent the gate spacer; a first inter-layer dielectric (ILD) on the source/drain region, the first ILD having a first concentration of an impurity; and a second ILD on the first ILD, the second ILD having a second concentration of the impurity, the second concentration being less than the first concentration, top surfaces of the second ILD, the gate spacer, and the gate structure being coplanar; and a source/drain contact extending through the second ILD and the first ILD, the source/drain contact coupled to the source/drain region.