In an embodiment, a device includes: a gate structure over a substrate; a gate spacer adjacent the gate structure; a source/drain region adjacent the gate spacer; a first inter-layer dielectric (ILD) on the source/drain region, the first ILD having a first concentration of an impurity; and a second ILD on the first ILD, the second ILD having a second concentration of the impurity, the second concentration being less than the first concentration, top surfaces of the second ILD, the gate spacer, and the gate structure being coplanar; and a source/drain contact extending through the second ILD and the first ILD, the source/drain contact coupled to the source/drain region.

Examples of the present technology include semiconductor processing methods that may include generating a plasma from a deposition precursor in a processing region of a semiconductor processing chamber. The plasma may be generated at a delivered power within a first period of time when plasma power is delivered from a power source operating at a first duty cycle. The methods may further include transitioning the power source from the first duty cycle to a second duty cycle after the first period of time. A layer may be deposited on a substrate in the processing region of the semiconductor processing chamber from the generated plasma. The layer, as deposited, may be characterized by a thickness of 50 Å or less. Exemplary deposition precursors may include one or more silicon-containing precursors, and an exemplary layer deposited on the substrate may include an amorphous silicon layer.

The present invention is to form an organic film on a substrate having a pattern formed on a front surface thereof and configured to: apply an organic material onto the substrate; then thermally treat the organic material to form an organic film on the substrate; and then perform ultraviolet irradiation processing on the organic film to remove a surface of the organic film down to a predetermined depth, thereby appropriately and efficiently form the organic film on the substrate.

The disclosed subject matter provides a p-channel metal-oxide-semiconductor (PMOS) and fabrication method thereof. The PMOS transistor is fabricated by a method including forming a dummy gate structure on a semiconductor substrate, forming a source region and a drain region in the semiconductor substrate on both sides of the dummy gate structure, forming an intermediate layer to cover the dummy gate structure and the semiconductor substrate, and forming a multiple-level etching stop layer including at least a first etching stop layer and a second etching stop layer. The fabrication method also includes performing a UV curing process after forming each of the first and second etching stop layers.

Plasma processing apparatus and associated methods are provided. In one example, a plasma processing apparatus includes a plasma chamber. The plasma processing apparatus includes a dielectric wall forming at least a portion of the plasma chamber. The plasma processing apparatus includes an inductive coupling element located proximate the dielectric wall. The plasma processing apparatus includes an ultraviolet light source configured to emit an ultraviolet light beam onto a metal surface that faces an interior volume of the plasma chamber. The plasma processing apparatus includes a controller configured to control the ultraviolet light source.

The present teachings relate to compositions for forming a negative-tone photopatternable dielectric material, where the compositions include, among other components, an organic filler and one or more photoactive compounds, and where the presence of the organic filler enables the effective removal of such photoactive compounds (after curing, and during or after the development step) which, if allowed to remain in the photopatterned dielectric material, would lead to deleterious effects on its dielectric properties.

A package structure includes a substrate and a package plate. A frame is formed of a seal glue arranged between the substrate and the package plate. An underfill is positioned inboard of the frame. The package plate has a spreading surface, and at least one groove is formed in a spreading path of the frame on the spreading surface of the package plate.

Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes providing a substrate, the substrate includes a first fin, a second fin, and an isolation region disposed between the first fin and the second fin. The second fin includes a different material than a material of the substrate. The method includes forming an oxide over the first fin, the second fin, and a top surface of the isolation region at a temperature of about 400 degrees C. or less, and post-treating the oxide at a temperature of about 600 degrees C. or less.

Methods and apparatuses suitable for depositing low hydrogen content, hermetic, thin encapsulation layers at temperatures less than about 300° C. are provided herein. Methods involve pulsing plasma while exposing a substrate to deposition reactants, and post-treating deposited encapsulation films to densify and reduce hydrogen content. Post-treatment methods include periodic exposure to inert plasma without reactants and exposure to ultraviolet radiation at a substrate temperature less than about 300° C.

Some embodiments include methods of forming structures. Spaced-apart features are formed which contain temperature-sensitive material. Liners are formed along sidewalls of the features under conditions which do not expose the temperature-sensitive material to a temperature exceeding 300° C. The liners extend along the temperature-sensitive material and narrow gaps between the spaced-apart features. The narrowed gaps are filled with flowable material which is cured under conditions that do not expose the temperature-sensitive material to a temperature exceeding 300° C. In some embodiments, the features contain memory cell regions over select device regions. The memory cell regions include first chalcogenide and the select device regions include second chalcogenide. The liners extend along and directly against the first and second chalcogenides.