Patent classifications
H01L21/02348
SEMICONDUCTOR DEVICE WITH CARBON HARD MASK AND METHOD FOR FABRICATING THE SAME
The present application discloses a semiconductor device with a carbon hard mask. The semiconductor device includes a substrate, conductive layers positioned on the substrate, a carbon hard mask layer positioned on the conductive layers, an insulating layer including a lower portion and an upper portion, and a conductive via positioned along the upper portion of the insulating layer and the carbon hard mask layer and positioned on one of the adjacent pair of the conductive layers. The lower portion is positioned along the carbon hard mask layer and positioned between an adjacent pair of the conductive layers, and the upper portion is positioned on the lower portion and on the carbon hard mask layer.
Precursors and flowable CVD methods for making low-k films to fill surface features
A method for depositing a silicon-containing film, the method comprising: placing a substrate comprising at least one surface feature into a flowable CVD reactor; introducing into the reactor at least one silicon-containing compound and at least one multifunctional organoamine compound to at least partially react the at least one silicon-containing compound to form a flowable liquid oligomer wherein the flowable liquid oligomer forms a silicon oxide coating on the substrate and at least partially fills at least a portion of the at least one surface feature. Once cured, the silicon carbonitride coating has excellent mechanical properties.
Masking layer with post treatment
A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.
Semiconductor device with tilted insulating layers and method for fabricating the same
The present disclosure relates to a semiconductor device with tilted insulating layers and a method for fabricating the semiconductor device with the tilted insulating layers. The semiconductor device includes a substrate, two conductive pillars positioned above the substrate and extended along a vertical axis, a first set of tilted insulating layers parallel to each other and positioned between the two conductive pillars, and a second set of tilted insulating layers parallel to each other and positioned between the two conductive pillars. The first set of tilted insulating layers are extended along a first direction slanted with respect to the vertical axis, the second set of tilted insulating layers are extended along a second direction slanted with respect to the vertical axis, and the first direction and the second direction are crossed.
Chuck assembly, planarization process, apparatus and method of manufacturing an article
A chuck assembly for holding a plate comprises a member configured to hold the plate, the member including a flexible portion configured to have a central opening, and a first cavity formed by the flexible portion, wherein the plate is held by the flexible portion by reducing pressure in the first cavity, a light-transmitting member covering the central opening of the member, and a fluid path in communication with a second cavity defined by the member, the plate held by the member and the light-transmitting member for pressurizing the second cavity.
Method for forming insulating film, apparatus for processing substrate, and system for processing substrate
There is provided a technique of forming an insulating film containing silicon oxide. A coating solution containing polysilazane is applied onto a wafer W, the solvent of the coating solution is volatilized, and the coating film is irradiated with ultraviolet rays in nitrogen atmosphere before performing a curing process. Dangling bonds are generated in silicon which is a pre-hydrolyzed site in polysilazane. Therefore, the energy for hydrolysis is reduced, and unhydrolyzed sites are reduced even when the temperature of the curing process is 350° C. Since efficient dehydration condensation occurs, the crosslinking rate is improved, and a dense (good-quality) insulation film is formed. By forming a protective film on the surface of the coating film to which ultraviolet rays irradiated, the reaction of dangling bonds prior to the curing process is suppressed.
METHODS FOR DEPOSITING GAP-FILLING FLUIDS AND RELATED SYSTEMS AND DEVICES
Methods and related systems for at least partially filling recesses comprised in a substrate with a gap filling fluid. The gap filling fluid comprises a Si—N bond. The methods comprise exposing the substrate to a nitrogen and hydrogen-containing gas on the one hand and to vacuum ultraviolet light on the other hand.
Display device with passivation layer that directly contacts the substrate and manufacturing method thereof
A display device includes: a substrate; a transistor disposed on a first surface of the substrate; and a passivation layer disposed on a second surface of the substrate opposite from the first surface, wherein the passivation layer directly contacts the substrate, and the passivation layer includes a UV curable resin.
WAFER PROCESS, APPARATUS AND METHOD OF MANUFACTURING AN ARTICLE
An apparatus is provided. The apparatus has a chuck having a first side configured to retain a superstrate or a template and a second side, an array of image sensors disposed at the second side of the chuck and spaced from the chuck, and an array of light sources disposed between the transparent chuck and the array of image sensors.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device includes an N-type fin-like field effect, a P-type fin-like field effect transistor, a shallow trench isolation (STI) structure, a first interlayer dielectric (ILD) layer, and a second ILD layer. The N-type fin-like field effect transistor includes a first semiconductor fin, a gate structure across the first semiconductor fin, and a first source/drain feature in contact with the first semiconductor fin. The P-type fin-like field effect transistor includes a second semiconductor fin, the gate structure across the second semiconductor fin, and a second source/drain feature in contact with the second semiconductor fin. The structure surrounds the first and second semiconductor fins. The first interlayer dielectric (ILD) layer covers the first source/drain feature. The second ILD layer covers the second source/drain feature, wherein a porosity of the second ILD layer is greater than a porosity of the first ILD layer.