A method may include providing a substrate, where the substrate includes a first main surface and a second main surface, opposite the first main surface. The second main surface may include a stress compensation layer. The method may include directing ions to the stress compensation layer in an ion implant procedure. The ion implant procedure may include exposing a first region of the stress compensation layer to a first implant process, wherein a second region of the stress compensation layer is not exposed to the first implant process.

A chemical vapor deposition method for producing a dielectric film, the method comprising: providing a substrate into a reaction chamber; introducing gaseous reagents into the reaction chamber wherein the gaseous reagents comprise a silicon precursor comprising an silicon compound having Formula I as defined herein and applying energy to the gaseous reagents in the reaction chamber to induce reaction of the gaseous reagents to deposit a film on the substrate. The film as deposited is suitable for its intended use without an optional additional cure step applied to the as-deposited film.

Described are boron-doped amorphous carbon hard masks, methods of preparing boron-doped amorphous carbon hard masks, methods of using the boron-doped amorphous carbon hard masks, and devices that include the boron-doped amorphous carbon hard masks.

The present disclosure provides systems and methods for processing channel structures of substrates that include positioning the substrate in a first processing chamber having a first processing volume being in fluid communication with a plasma source. The substrate can include a channel structure with high aspect ratio features having aspect ratios greater than about 20:1. The method can also include forming an oxide cap layer over a silicon-containing layer of the channel structure and exposing the oxide cap layer to a hydrogen-or-deuterium radical to nucleate the silicon-containing layer of the channel structures of the substrate. Forming the oxide cap layer and exposing the channel structure with the hydrogen radical occurs in the first processing chamber to form a nucleated substrate. The method can also include positioning the nucleated substrate in a second processing chamber with a second processing volume and heating the nucleated substrate in the second processing chamber.

The present disclosure provides systems and methods for processing channel structures of substrates that include positioning the substrate in a first processing chamber having a first processing volume. The substrate includes a channel structure with high aspect ratio features having aspect ratios greater than about 20:1. The method includes forming a silicon-containing layer over the channel structure to a hydrogen-or-deuterium plasma in the first processing volume at a flow rate of about 10 sccm to about 5000 sccm. The substrate is maintained at a temperature of about 100° C. to about 1100° C. during the exposing, the exposing forming a nucleated substrate. Subsequent to the exposing a thermal anneal operation is performed on the substrate.

A semiconductor device is disclosed in which proton implantation is performed a plurality of times to form a plurality of n-type buffer layers in an n-type drift layer at different depths from a rear surface of a substrate. The depth of the n-type buffer layer, which is provided at the deepest position from the rear surface of the substrate, from the rear surface of the substrate is more than 15 μm. The temperature of a heat treatment which is performed in order to change a proton into a donor and to recover a crystal defect after the proton implantation is equal to or higher than 400° C. In a carrier concentration distribution of the n-type buffer layer, a width from the peak position of carrier concentration to an anode is more than a width from the peak position to a cathode.

A semiconductor structure and a formation method thereof are provided. In one form, the method includes: providing a base; patterning the base to form a substrate and discrete fins and pseudo fins which protrude from the substrate, wherein the fins are located in a device region, and the pseudo fins are located in isolation regions; removing the pseudo fins in the isolation regions; forming isolation layers on the substrate exposed by the fins, wherein the isolation layers cover part of the side walls of the fins; and thinning the isolation layers in the isolation regions, wherein the remaining isolation layers in the isolation regions are regarded as target isolation layers, and the surfaces of the target isolation layers are lower than the surfaces of the isolation layers between the discrete fins. Since the surfaces of the target isolation layers are lower than the surfaces of the isolation layers between the discrete fins, the volume of the target isolation layers is correspondingly reduced, and then stress generated by the target isolation layers on the fins is lowered, which causes the stress on both sides of the fins to be balanced, avoids the problem of bending or tilting of the fins in the device region in case of stress imbalance and improves the electrical performance of the semiconductor structure.

A method includes depositing an etch stop layer over a first conductive feature, performing a first treatment to amorphize the etch stop layer, depositing a dielectric layer over the n etch stop layer, etching the dielectric layer to form an opening, etching-through the etch stop layer to extend the opening into the etch stop layer, and filling the opening with a conductive material to form a second conductive feature.

A method for doping a layer, a thin film transistor and a method for fabricating the thin film transistor. The method comprises: forming a layer to be doped on a substrate by a first patterning process, wherein the layer comprises a first region, a second region and a third region, the first region is arranged in a middle region, the third region is arranged in an edge region, the second region is arranged between the first region and the third region; forming a first blocking layer and a second blocking layer on the layer in this order by a second patterning process, wherein an orthographic projection region of the first blocking layer on the layer exactly covers the first region, and an orthographic projection region of the second blocking layer on the layer exactly covers the first region and the second region; perform a first doping on the layer with an ion beam perpendicular to the substrate, to realize doping of the third region; rotating the substrate by a preset angle in a direction parallel to the ion beam, so that the second blocking layer does not shield the second region, and performing a second doping on the layer with the ion beam.

A semiconductor structure and a formation method thereof are provided. In one form, the method includes: providing a base; patterning the base to form a substrate and discrete fins and pseudo fins which protrude from the substrate, wherein the fins are located in a device region, and the pseudo fins are located in isolation regions; removing the pseudo fins in the isolation regions; forming isolation layers on the substrate exposed by the fins, wherein the isolation layers cover part of the side walls of the fins; and thinning the isolation layers in the isolation regions, wherein the remaining isolation layers in the isolation regions are regarded as target isolation layers, and the surfaces of the target isolation layers are lower than the surfaces of the isolation layers between the discrete fins. Since the surfaces of the target isolation layers are lower than the surfaces of the isolation layers between the discrete fins, the volume of the target isolation layers is correspondingly reduced, and then stress generated by the target isolation layers on the fins is lowered, which causes the stress on both sides of the fins to be balanced, avoids the problem of bending or tilting of the fins in the device region in case of stress imbalance and improves the electrical performance of the semiconductor structure.