Provided are methods of reducing the stress of a semiconductor wafer. A wafer map of a free-standing wafer is created using metrology tools. The wafer map is then converted into a power spectral density (PSD) using a spatial frequency scale. The fundamental component of bow is then compensated with a uniform film, e.g., silicon nitride (SiN), deposited on the back side of the wafer.

A multi-level interconnect structure is formed on a semiconductor wafer to include conductive interconnect structures formed over an interconnect region and capacitor-terminal structures formed over a capacitor region by selectively implanting one or more inter-layer dielectric (ILD) layers over the interconnect region with a capacitance-reducing implant species while protecting each ILD layer over the capacitor region from the capacitance-reducing implant species, thereby forming a relatively lower-capacitance interconnect structure over the interconnect region and a relatively higher-capacitance capacitor over the capacitor region.

Methods and apparatus for forming an integrated circuit structure, comprising: delivering a process gas to a process volume of a process chamber; applying low frequency RF power to an electrode formed from a high secondary electron emission coefficient material disposed in the process volume; generating a plasma comprising ions in the process volume; bombarding the electrode with the ions to cause the electrode to emit electrons and form an electron beam; and contacting a dielectric material with the electron beam to cure the dielectric material, wherein the dielectric material is a flowable chemical vapor deposition product. In embodiments, the curing stabilizes the dielectric material by reducing the oxygen content and increasing the nitrogen content of the dielectric material.

A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.

Gate fabrication techniques are disclosed herein for providing gate stacks and/or gate structures (e.g., high-k/metal gates) with improved profiles (e.g., minimal to no warping, bending, bowing, and necking and/or substantially vertical sidewalls), which may be implemented in various device types. For example, gate fabrication techniques disclosed herein provide gate stacks with stress-treated glue layers having a residual stress that is less than about 1.0 gigapascals (GPa) (e.g., about 2.5 GPa to about 0.8 GPa). In some embodiments, a stress-treated glue layer is provided by depositing a glue layer over a work function layer and performing a stress reduction treatment, such as an ion implantation process and/or an annealing process in a gas ambient, on the glue layer. In some embodiments, a stress-treated glue layer is provided by forming at least one glue sublayer/metal layer pair over a work function layer, performing a poisoning process, and forming a glue sublayer over the pair.