A method includes forming an under bump metallization (UBM) layer over a dielectric layer, forming a redistribution structure over the UBM layer, disposing a semiconductor device over the redistribution structure, removing a portion of the dielectric layer to form an opening to expose the UBM layer, and forming a conductive bump in the opening such that the conductive bump is coupled to the UBM layer.

In a method of manufacturing a semiconductor device, a plurality of pattern structures disposed on a substrate and having sidewall surfaces extending in a direction perpendicular to a surface of the substrate are provided. An amorphous dielectric layer is formed on at least the sidewall surfaces of the plurality of pattern structures. A plurality of metal particles are distributed on the amorphous dielectric layer. A first crystalline dielectric layer by thermally treating the amorphous dielectric layer using laser light. In thermally treating the amorphous dielectric layer, the laser light is irradiated onto the amorphous dielectric layer from upper sides of the plurality of pattern structures, wherein the irradiated laser light is scattered from the plurality of metal particles.

A method of semiconductor device fabrication includes providing a substrate having a hardmask layer thereover. The hardmask layer is patterned to expose the substrate. The substrate is etched through the patterned hardmask layer to form a first fin element and a second fin element extending from the substrate. An isolation feature between the first and second fin elements is formed, where the isolation feature has a first etch rate in a first solution. A laser anneal process is performed to irradiate the isolation feature with a pulsed laser beam. A pulse duration of the pulsed laser beam is adjusted based on a height of the isolation feature. The isolation feature after performing the laser anneal process has a second etch rate less than the first etch rate in the first solution.

A package structure includes a semiconductor device, a first dielectric layer, a redistribution line and a conductive bump. The first dielectric layer is over the semiconductor device and has first and second openings on opposite surfaces of the first dielectric layer, wherein the first and second openings taper in substantially opposite direction. The redistribution line is partially in the first opening of the first dielectric layer and electrically connected to the semiconductor device. The conductive bump is partially embeddedly retained in the second opening and electrically connected to the redistribution line.

A wafer processing method includes a circular recess forming step of forming a circular recess in a center of a back surface of a wafer to thereby form an annular projection surrounding the circular recess, and a modified layer forming step of applying a laser beam of such a wavelength as to be transmitted through the wafer to the annular projection to thereby form a modified layer.

Described herein are compositions and methods using same for forming a silicon-containing film such as, without limitation, a carbon doped silicon oxide film, a carbon doped silicon nitride, a carbon doped silicon oxynitride film in a deposition process. In one aspect, the composition comprises at least cyclic carbosilane having at least one SiCSi linkage and at least one anchoring group selected from a halide atom, an amino group, and combinations thereof.

A semiconductor process including the following steps is provided. A wafer is provided. The wafer has a front side and a back side. The wafer has a semiconductor device on the front side. A protection layer is formed on the front side of the wafer. The protection layer covers the semiconductor device. A material of the protection layer includes a photoresist material. A surface hardening treatment process is performed on the protection layer. A first patterning process is performed on the back side of the wafer. The semiconductor process can effectively protect the front side of the wafer during a backside process.

Embodiments disclosed herein generally relate to methods and apparatus for processing of the bottom surface of a substrate to counteract thermal stresses thereon. Correcting strains are applied to the bottom surface of the substrate which compensate for undesirable strains and distortions on the top surface of the substrate. Specifically designed films may be formed on the back side of the substrate by any combination of deposition, implant, thermal treatment, and etching to create strains that compensate for unwanted distortions of the substrate. Localized strains may be introduced by locally altering the hydrogen content of a silicon nitride film or a carbon film. Structures may be formed by printing, lithography, or self-assembly techniques. Treatment of the layers of film is determined by the stress map desired and includes annealing, implanting, melting, or other thermal treatments.

A method of semiconductor device fabrication includes providing a substrate having a hardmask layer thereover. The hardmask layer is patterned to expose the substrate. The substrate is etched through the patterned hardmask layer to form a first fin element and a second fin element extending from the substrate. An isolation feature between the first and second fin elements is formed, where the isolation feature has a first etch rate in a first solution. A laser anneal process is performed to irradiate the isolation feature with a pulsed laser beam. A pulse duration of the pulsed laser beam is adjusted based on a height of the isolation feature. The isolation feature after performing the laser anneal process has a second etch rate less than the first etch rate in the first solution.

A semiconductor package includes a substrate, a semiconductor element disposed on the substrate, an encapsulating layer covering side surfaces and a top surface of the semiconductor element, an electromagnetic shield layer covering side surfaces of the substrate and side surfaces and a top surface of the encapsulating layer, and a titanium oxide layer formed above a top surface of the electromagnetic shield layer, and including a first portion containing divalent titanium oxide and a second portion containing tetravalent titanium oxide.