H01L21/02376

METHODS OF FORMING SOI SUBSTRATES

Methods of forming SOI substrates are disclosed. In some embodiments, an epitaxial layer and an oxide layer are formed on a sacrificial substrate. An etch stop layer is formed in the epitaxial layer. The sacrificial substrate is bonded to a handle substrate at the oxide layer. The sacrificial substrate is removed. The epitaxial layer is partially removed until the etch stop layer is exposed.

Diamond substrate producing method
10950462 · 2021-03-16 · ·

A diamond substrate producing method includes a belt-shaped separation layer forming step of applying a laser beam to a diamond ingot as relatively moving the ingot and a focal point of the laser beam in a [110]-direction perpendicular to a (110)-plane, thereby forming a belt-shaped separation layer extending in the [110]-direction inside the ingot, an indexing step of relatively moving the ingot and the focal point in an indexing direction parallel to a (001)-plane and perpendicular to the [110]-direction, a planar separation layer forming step of repeating the belt-shaped separation layer forming step and the indexing step to thereby form a planar separation layer parallel to the (001)-plane inside the ingot, the planar separation layer being composed of a plurality of belt-shaped separation layers arranged side by side in the indexing direction, and a separating step of separating a substrate from the diamond ingot along the planar separation layer.

METHOD OF FORMING TRANSITION METAL DICHALCOGENIDE THIN FILM

Disclosed herein are a method of forming a transition metal dichalcogenide thin film and a method of manufacturing a device including the same. The method of forming a transition metal dichalcogenide thin film includes: providing a substrate in a reaction chamber; depositing a transition metal dichalcogenide thin film on the substrate using a sputtering process that uses a transition metal precursor and a chalcogen precursor and is performed at a first temperature; and injecting the chalcogen precursor in a gas state and heat-treating the transition metal dichalcogenide thin film at a second temperature that is higher than the first temperature. The substrate may include a sapphire substrate, a silicon oxide (SiO.sub.2) substrate, a nanocrystalline graphene substrate, or a molybdenum disulfide (MoS.sub.2) substrate.

STACK COMPRISING SINGLE-CRYSTAL DIAMOND SUBSTRATE

There is provided a novel stack that includes a single-crystal diamond substrate having a coalescence boundary, yet effectively uses the coalescence boundary. A stack comprising at least a semiconductor drift layer stacked on a single-crystal diamond substrate having a coalescence boundary, wherein the coalescence boundary of the single-crystal diamond substrate is a region that exhibits, in a Raman spectrum at a laser excitation wavelength of 785 nm, a full width at half maximum of a peak near 1332 cm.sup.1 due to diamond that is observed to be broader than a full width at half maximum of the peak exhibited by a region different from the coalescence boundary, the coalescence boundary has a width of 200 m or more, and the semiconductor drift layer is stacked on at least the coalescence boundary.

METHODS FOR FORMING LARGE AREA DIAMOND SUBSTRATES
20210214856 · 2021-07-15 ·

The disclosure relates to large area single crystal diamond (SCD) surfaces and substrates, and their methods of formation. Typical large area substrates can be at least about 25 mm, 50 mm, or 100 mm in diameter or square edge length, and suitable thicknesses can be about 100 m to 1000 m. The large area substrates have a high degree of crystallographic alignment. The large area substrates can be used in a variety of electronics and/or optics applications. Methods of forming the large area substrates generally include lateral and vertical growth of SCD on spaced apart and crystallographically aligned SCD seed substrates, with the individual SCD growth layers eventually merging to form a composite SCD layer of high quality and high crystallographic alignment. A diamond substrate holder can be used to crystallographically align the SCD seed substrates and reduce the effect of thermal stress on the formed SCD layers.

Device, system, and method for selectively tuning nanoparticles with graphene

A graphene device for filtering color, involving a graphene structure responsive to continuous in-situ electrical gate-tuning of a Fermi level thereof and a plurality of nanoparticles disposed in relation to the graphene structure, each portion of the plurality of nanoparticles having a distinct energy bandgap in relation to another portion of the plurality of nanoparticles, and each portion of the plurality of nanoparticles configured to one of activate and deactivate in relation to the distinct energy bandgap and in response to the in-situ electrical gate-tuning of the Fermi level of the graphene structure.

COMPOSITE SUBSTRATE, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR DEVICE
20240006257 · 2024-01-04 · ·

Disclosed are a composite substrate, a manufacturing method thereof and a semiconductor device. The composite substrate includes a first substrate, a bonding layer, and a second substrate which are stacked sequentially, where the first substrate comprises a plurality of protruding structures disposed on a side close to the second substrate, and a groove formed between at least two protruding structures of the plurality of protruding structures. The composite substrate provided by the present disclosure, by setting a bonding layer, a bond strength between the first substrate and the second substrate may be improved, and a mechanical strength of the composite substrate is enhanced. By setting the groove, a stress transmitted from the second substrate to the first substrate may be attenuated, so as to improve the mechanical strength of the composite substrate and avoid a plastic deformation in a subsequent epitaxial process.

SiC epitaxial wafer, manufacturing apparatus of SiC epitaxial wafer, fabrication method of SiC epitaxial wafer, and semiconductor device
10876220 · 2020-12-29 · ·

A SiC epitaxial wafer includes: a substrate having an off angle of less than 4 degrees; and a SiC epitaxial growth layer disposed on the substrate having the off angle of less than 4 degrees, wherein an Si compound is used for a supply source of Si, and a C compound is used as a supply source of C, for the SiC epitaxial growth layer, wherein the uniformity of carrier density is less than 10%, and the defect density is less than 1 count/cm.sup.2; and a C/Si ratio of the Si compound and the C (carbon) compound is within a range of 0.7 to 0.95. There is provide a high-quality SiC epitaxial wafer excellent in film thickness uniformity and uniformity of carrier density, having the small number of surface defects, and capable of reducing costs, also in low-off angle SiC substrates on SiC epitaxial growth.

Method of fabricating electrically isolated diamond nanowires and its application for nanowire MOSFET
10879358 · 2020-12-29 · ·

A method for fabricating an electrically isolated diamond nanowire includes forming a diamond nanowire on a diamond substrate, depositing a dielectric or a polymer on the diamond nanowire and on the diamond substrate, planarizing the dielectric or the polymer, etching a portion of the planarized dielectric or polymer to expose a first portion of the diamond nanowire, depositing a metal layer to conformably cover the first portion of the diamond nanowire, and implanting ions into a second portion of the diamond nanowire between the first portion of the diamond nanowire and the diamond substrate or at an intersection of the diamond nanowire and the diamond substrate, wherein the ions are implanted at an oblique angle from a first side of the diamond nanowire.

Device, System, and Method for Selectively Tuning Nanoparticles with Graphene

A graphene device for filtering color, involving a graphene structure responsive to continuous in-situ electrical gate-tuning of a Fermi level thereof and a plurality of nanoparticles disposed in relation to the graphene structure, each portion of the plurality of nanoparticles having a distinct energy bandgap in relation to another portion of the plurality of nanoparticles, and each portion of the plurality of nanoparticles configured to one of activate and deactivate in relation to the distinct energy bandgap and in response to the in-situ electrical gate-tuning of the Fermi level of the graphene structure.