A structure includes a stepped crystalline substrate that includes an upper step, a lower step, and a step rise. A first fin includes a crystalline structure having a first lattice constant. The first fin is formed over the lower step. A second fin includes a crystalline structure having a second lattice constant, the second lattice constant being different than the first lattice constant. The second fin can be formed over the upper step apart from the first fin. A second crystalline structure can be formed over the first crystalline structure and the tops of the fins aligned. The first and second fins can be made of the same material, but with different heights and different channel strain values. The first fin can be used as an NMOS fin and the second fin can be used as a PMOS fin of a CMOS FinFET.

A method for forming a Ga-doped SiGe layer comprises depositing, in the presence of a C-containing Ga precursor, Ga-doped SiGe on a substrate, thereby forming a first portion of the Ga-doped SiGe layer. The method further comprises depositing, in the absence of the C-containing Ga precursor, SiGe on the first portion, thereby forming a second portion of the Ga-doped SiGe layer.

Provided is an electronic device including a semiconductor substrate, a single-crystal first transition metal oxide layer on the semiconductor substrate, and a single-crystal second transition metal oxide layer spaced apart from the semiconductor substrate with the single-crystal first transition metal oxide layer interposed therebetween. The first transition metal oxide layer and the second transition metal oxide layer are in contact with each other. The semiconductor substrate, the first transition metal oxide layer, and the second transition metal oxide layer include different materials from each other. The first transition metal oxide layer and the second transition metal oxide layer have the same crystal direction.

A method of fabricating a device involves forming a plurality of structures, such that each structure of the plurality includes a substrate and an epitaxial layer on the substrate. The epitaxial layer and the substrate have a lattice mismatch. The method further includes forming an electrical contact on the epitaxial layer of a selected structure of the plurality of structures and performing a current leakage measurement quality control test for the selected structure of the plurality of structures through the electrical contact. The method also involves forming a device on each of the remaining structures of the plurality of structures if the selected structure passed the leakage measurement quality control test or discarding each of the remaining structures of the plurality of structures if the selected structure did not pass the leakage measurement quality control test.

The present disclosure describes a method for controlling radiation conditions and an example system for performing the method. The method includes sending a first setting to configure a radiation device to provide radiation to a substrate undergoing a process operation in a process chamber of the radiation device. The method further includes receiving radiation energy data measured at a plurality of locations of the process chamber and receiving measurement data measured on the substrate during the process operation. The method further includes in response to a variance of the radiation energy data being above a first predetermined threshold and in response to a difference between reference data and the measurement data being above a second predetermined threshold, sending a second setting to configure the radiation device to provide radiation to the substrate.

A semiconductor device includes a semiconductor fin protruding from a substrate, a gate electrode over the semiconductor fin, a gate insulating layer between the semiconductor fin and the gate electrode, source and drain regions disposed on opposite sides of the semiconductor fin, a first stressor formed in a region between the source and drain regions. The first stressor including one material selected from the group consisting of He, Ne, and Ga.

A wafer carrier includes a pocket sized and shaped to accommodate a wafer, the pocket having a base and a substantially circular perimeter, and a removable orientation marker, the removable orientation marker comprising an outer surface and an inner surface, the outer surface having an arcuate form sized and shaped to mate with the substantially circular perimeter of the pocket, and the inner surface comprising a flat face, wherein the removable orientation marker further comprises a notch at a first end of the flat face.

A method deposits an epitaxial layer on a front side of a semiconductor wafer having monocrystalline material. The method includes: providing the semiconductor wafer; arranging the semiconductor wafer on a susceptor; heating the semiconductor wafer to a deposition temperature using thermal radiation directed to the front side and to the rear side of the semiconductor wafer; conducting a deposition gas over the front side of the semiconductor wafer; and selectively reducing an intensity of a portion of the thermal radiation that is directed to the rear side of the semiconductor wafer, as a result of which first partial regions at an edge of the semiconductor wafer, in the first partial regions a growth rate of the epitaxial layer is greater than in adjacent second partial regions given uniform temperature of the semiconductor wafer owing to an orientation of the monocrystalline material, are heated more weakly.

Methods for determining suitability of a silicon substrate for epitaxy and/or for determining slip resistance during epitaxy and post-epitaxy thermal treatment are disclosed. The methods involve evaluating different substrates of the epitaxial wafers by imaging the wafer by infrared depolarization. An infrared depolarization parameter is generated for each epitaxial wafer. The parameters may be compared to determine which substrates are well-suited for epitaxial and/or post-epi heat treatments.

The present disclosure generally relates to bilayer metal dichalcogenides, to processes for forming bilayer metal dichalcogenides, and to uses of bilayer metal dichalcogenides in devices for quantum electronics. In an aspect, a device is provided. The device includes a gate electrode, a substrate disposed over at least a portion of the gate electrode, and a bottom layer including a first metal dichalcogenide, the bottom layer disposed over at least a portion of the substrate. The device further includes a top layer including a second metal dichalcogenide, the top layer disposed over at least a portion of the bottom layer, the first metal dichalcogenide and the second metal dichalcogenide being the same or different. The device further includes a source electrode and a drain electrode disposed over at least a portion of the top layer.