A method for manufacturing a vertical JFET includes providing a III-nitride substrate having a first conductivity type and forming a first III-nitride layer coupled to the III-nitride substrate. The first III-nitride layer is characterized by a first dopant concentration and the first conductivity type. The method also includes forming a plurality of trenches within the first III-nitride layer and epitaxially regrowing a second III-nitride structure in the trenches. The second III-nitride structure is characterized by a second conductivity type. The method further includes forming a plurality of III-nitride fins, each coupled to the first III-nitride layer, wherein the plurality of III-nitride fins are separated by one of a plurality of recess regions, and epitaxially regrowing a III-nitride gate layer in the recess regions. The III-nitride gate layer is coupled to the second III-nitride structure and the III-nitride gate layer is characterized by the second conductivity type.

A nitride semiconductor laminate includes: a substrate comprising a group III nitride semiconductor and including a surface and a reverse surface, the surface being formed from a nitrogen-polar surface, the reverse surface being formed from a group III element-polar surface and being provided on the reverse side from the surface; a protective layer provided at least on the reverse surface side of the substrate and having higher heat resistance than the reverse surface of the substrate; and a semiconductor layer provided on the surface side of the substrate and comprising a group III nitride semiconductor. The concentration of O in the semiconductor layer is lower than 1×10.sup.17 at/cm.sup.3.

The present disclosure relates to a semiconductor substrate manufacturing method including: forming a catalytic metal film composed of a transition metal on a main surface to be polished of a workpiece substrate composed of any one of diamond, silicon carbide, gallium nitride, and sapphire; and providing relative movement between the workpiece substrate on which the catalytic metal film has been formed and a polishing platen in an oxidant solution to remove a compound generated by chemical reaction of an active radical generated by reaction of the catalytic metal film and the oxidant solution and a surface atom on the main surface of the workpiece substrate to thereby polish the workpiece substrate. The manufacturing method further includes: bonding the polished workpiece substrate to a nitride semiconductor layer by room temperature bonding; and removing a support substrate and a resin adhesive layer.

Epitaxial growth of materials, and related systems and articles, are generally described.

An object is to provide a nonpolar or semipolar GaN substrate having improved size and crystal quality. A self-standing GaN substrate has an angle between the normal of the principal surface and an m-axis of 0 degrees or more and 20 degrees or less, wherein: the size of the projected image in a c-axis direction when the principal surface is vertically projected on an M-plane is 10 mm or more; and when an a-axis length is measured on an intersection line between the principal surface and an A-plane, a low distortion section with a section length of 6 mm or more and with an a-axis length variation within the section of 10.0×10.sup.−5 Å or less is observed.

Semiconductor structures and methods for forming those semiconductor structures are disclosed. For example, a semiconductor structure with a p-type superlattice region, an i-type superlattice region, and an n-type superlattice region is disclosed. The semiconductor structure can have a polar crystal structure with a growth axis that is substantially parallel to a spontaneous polarization axis of the polar crystal structure. In some cases, there are no abrupt changes in polarisation at interfaces between each region. At least one of the p-type superlattice region, the i-type superlattice region and the n-type superlattice region can comprise a plurality of unit cells exhibiting a monotonic change in composition from a wider band gap (WBG) material to a narrower band gap (NBG) material or from a NBG material to a WBG material along the growth axis to induce p-type or n-type conductivity.

A method for producing an aluminium nitride (AlN)-based layer on a structure with the basis of silicon (Si) or with the basis of a III-V material, may include several deposition cycles performed in a plasma reactor comprising a reaction chamber inside which is disposed a substrate having the structure. Each deposition cycle may include at least the following: deposition of aluminium-based species on an exposed surface of the structure, the deposition including at least one injection into the reaction chamber of an aluminium (Al)-based precursor; and nitridation of the exposed surface of the structure, the nitridation including at least one injection into the reaction chamber of a nitrogen (N)-based precursor and the formation in the reaction chamber of a nitrogen-based plasma. During the formation of the nitrogen-based plasma, a non-zero polarisation voltage V.sub.bias_.sub.substrate may be applied to the substrate.

Embodiments of the present application provide a semiconductor structure and a manufacturing method therefor. A buffer layer is disposed on a substrate layer, and the buffer layer includes a first buffer layer and a second buffer layer. By doping a transition metal in the first buffer layer, a deep level trap may be formed to capture background electrons, and diffusion of free electrons toward the substrate may also be avoided. By decreasing a doping concentration of the transition metal in the second buffer layer, a tailing effect is avoided and current collapse is prevented. By doping periodically the impurity in the buffer layer, the impurity may be as an acceptor impurity to compensate the background electrons, and then a concentration of the background electrons is reduced. By using the periodic doping method, dislocations, caused by doping, in the buffer layer may be effectively reduced.

The present invention provides a nitride semiconductor substrate suitable for a high frequency device. The nitride semiconductor substrate has a substrate, a buffer layer made of group 13 nitride semiconductors, and an active layer made of group 13 nitride semiconductors in this order, wherein the substrate is composed of a first substrate made of polycrystalline aluminum nitride, and a second substrate made of Si single crystal having a specific resistance of 100 Ω.Math.cm or more, formed on the first substrate, the average particle size of AlN constituting the first substrate is 3 to 9 μm, and preferably, the second substrate grown by the MCZ method has an oxygen concentration of 1E+18 to 9E+18 atoms/cm.sup.3 and a specific resistance of 100 to 1000 Ω.Math.cm.

A method of performing heteroepitaxy comprises exposing a substrate to a carrier gas, a first precursor gas, a Group II/III element, and a second precursor gas, to form a heteroepitaxial growth of one of GaAs, AlAs, InAs, GaP, InP, ZnSe, GaSe, CdSe, InSe, ZnTe, CdTe, GaTe, HgTe, GaSb, InSb, AlSb, CdS, GaN, and AlN on the substrate; wherein the substrate comprises one of GaAs, AlAs, InAs, GaP, InP, ZnSe, GaSe, CdSe, InSe, ZnTe, CdTe, GaTe, HgTe, GaSb, InSb, AlSb, CdS, GaN, and AlN; wherein the carrier gas is H.sub.2, wherein the first precursor is HCl, the Group II/III element comprises at least one of Zn, Cd, Hg, Al, Ga, and In; and wherein the second precursor is one of AsH.sub.3 (arsine), PH.sub.3 (phosphine), H.sub.2Se (hydrogen selenide), H.sub.2Te (hydrogen telluride), SbH.sub.3 (hydrogen antimonide), H.sub.2S (hydrogen sulfide), and NH.sub.3 (ammonia). The process may be an HVPE (hydride vapor phase epitaxy) process.