According to one embodiment, a nitride crystal includes first, second, and third nitride crystal regions. The third nitride crystal region includes Al, and is provided between the first and second nitride crystal regions. A third oxygen concentration in the third nitride crystal region is greater than a first oxygen concentration in the first nitride crystal region and greater than a second oxygen concentration in the second nitride crystal region. A third carbon concentration in the third nitride crystal region is greater than a first carbon concentration in the first nitride crystal region and greater than a second carbon concentration in the second nitride crystal region. A <0001> direction of the first nitride crystal region is one of a first orientation from the second nitride crystal region toward the first nitride crystal region or a second orientation from the first nitride crystal region toward the second nitride crystal region.

A nonpolar III-nitride film grown on a miscut angle of a substrate, in order to suppress the surface undulations, is provided. The surface morphology of the film is improved with a miscut angle towards an a-axis direction comprising a 0.15° or greater miscut angle towards the a-axis direction and a less than 30° miscut angle towards the a-axis direction.

Provides is a C-plane GaN substrate which, although formed from a GaN crystal grown so that surface pits are generated, is free from any inversion domain, and moreover, has a low spiral dislocation density in a gallium polar surface. Provides is a C-plane GaN substrate wherein: the substrate comprises a plurality of facet growth areas each having a closed ring outline-shape on a gallium polar surface; the spiral dislocation density is less than 1×10.sup.6 cm.sup.−2 anywhere on the gallium polar surface; and the substrate is free from any inversion domain. The C-plane GaN substrate may comprise a high dislocation density part having a dislocation density of more than 1×10.sup.7 cm.sup.−2 and a low dislocation density part having a dislocation density of less than 1×10.sup.6 cm.sup.−2 on the gallium polar surface.

A gallium nitride substrate comprising a first main surface and a second main surface opposite thereto, wherein the first main surface is a non-polar or semi-polar plane, a dislocation density measured by a room-temperature cathode luminescence method in the first main surface is 1×10.sup.4 cm.sup.−2 or less, and an averaged dislocation density measured by a room-temperature cathode luminescence method in an optional square region sizing 250 μm×250 μm in the first main plan is 1×10.sup.6 cm.sup.−2 or less.

A semiconductor substrate is provided. The semiconductor substrate includes a ceramic base, a seed layer, and a nucleation layer. The ceramic base has a front surface and a back surface, and the front surface is a non-flat surface. The seed layer is disposed on the front surface of the ceramic substrate. The nucleation layer is disposed on the seed layer.

An apparatus for manufacturing a group III nitride single crystal including: a reaction vessel including a reaction area, wherein in the reaction area, a group III source gas and a nitrogen source gas are reacted such that a group III nitride crystal is grown on a substrate; a susceptor arranged in the reaction area and supporting the substrate; a group III source gas supply nozzle supplying the group III source gas to the reaction area; and a nitrogen source gas supply nozzle supplying the nitrogen source gas to the reaction area, wherein the nitrogen source gas supply nozzle is configured to supply the nitrogen source gas and at least one halogen-based gas selected from the group consisting of a hydrogen halide gas and a halogen gas to the reaction area.

In various embodiments, controlled heating and/or cooling conditions are utilized during the fabrication of aluminum nitride single crystals and aluminum nitride bulk polycrystalline ceramics. Thermal treatments may also be utilized to control properties of aluminum nitride crystals after fabrication.

In a manufacturing method of a semiconductor element of the present disclosure, a first semiconductor part (SL1) includes a protruding portion (TS) protruding toward an underlying substrate (UK), the protruding portion contains a nitride semiconductor, the protruding portion and the underlying substrate are bonded to each other, a semiconductor substrate (HK) includes a hollow portion (TK) located between the underlying substrate and the first semiconductor part, the hollow portion is in contact with a side surface of the protruding portion and communicates with the outside of the semiconductor substrate, and the protruding portion (TS) is irradiated with the laser beam (LZ) before the first semiconductor part is separated from the semiconductor substrate.

Embodiments of the present disclosure include techniques related to techniques for processing materials for manufacture of group-III metal nitride and gallium based substrates. More specifically, embodiments of the disclosure include techniques for substrates with a controlled oxygen gradient using a combination of processing techniques. Merely by way of example, the disclosure can be applied to growing crystals of GaN, AlN, InN, InGaN, AlGaN, and AlInGaN, and others for manufacture of bulk or patterned substrates. Such bulk or patterned substrates can be used for a variety of applications including optoelectronic and electronic devices, lasers, light emitting diodes, solar cells, photo electrochemical water splitting and hydrogen generation, photodetectors, integrated circuits, and transistors, and others.

A III-N semiconductor channel is compositionally graded between a transition layer and a III-N polarization layer. In embodiments, a gate stack is deposited over sidewalls of a fin including the graded III-N semiconductor channel allowing for formation of a transport channel in the III-N semiconductor channel adjacent to at least both sidewall surfaces in response to a gate bias voltage. In embodiments, a gate stack is deposited completely around a nanowire including a III-N semiconductor channel compositionally graded to enable formation of a transport channel in the III-N semiconductor channel adjacent to both the polarization layer and the transition layer in response to a gate bias voltage.