A method of manufacturing a semiconductor optical device of this disclosure includes the steps of forming an etch stop layer on an InP growth substrate, the etch stop layer having a thickness of 100 nm or less; and forming a semiconductor laminate on the etch stop layer by stacking a plurality of InGaAsP-based III-V group compound semiconductor layers containing at least In and P. Further, an intermediate article of a semiconductor optical device of the present disclosure includes an InP growth substrate; an etch stop layer formed on the InP growth substrate, the etch stop layer having a thickness of 100 nm or less; and a semiconductor laminate formed on the etch stop layer, including a plurality of InGaAsP-based III-V group compound semiconductor layers containing at least In and P stacked one another.

A method includes obtaining a semiconductor wafer having an orientation in a plane; depositing one or more masks to a semiconductor wafer, wherein each mask is configured to cover a portion of the semiconductor wafer, and wherein each mask includes a perimeter having multiple sides that are substantially aligned along a preferred crystal direction relative to the orientation that provides reduced or enhanced growth enhancement at edges of the substantially aligned sides; and performing Selective Area Epitaxy (SAE) growth on a surface of the semiconductor wafer, wherein the one or more masks inhibit the SAE growth over the associated portion.

Embodiments including apparatus, systems, and methods for nanofabrication are provided. In one example, a method of manufacturing a semiconductor device includes forming a two-dimensional (2D) layer comprising a 2D material on a first substrate and forming a plurality of holes in the 2D layer to create a patterned 2D layer. The method also includes forming a single-crystalline film on the patterned 2D layer and transferring the single-crystalline film onto a second substrate.

The disclosure concerns fabricating a quantum device. In an embodiment, a method is disclosed comprising: providing a substrate and an insulator formed on the substrate; from combinations of selective-area-grown semiconductor material along with regions of a superconducting material, forming a network of nanowires oriented in a plane of the substrate which can be used to produce a Majorana-based topological qubit; and fabricating a side gate for controlling a topological segment of the qubit; wherein the selective-area-grown semiconductor material is grown on the substrate, by etching trenches in the insulator formed on the substrate to define the nanowires and depositing the semiconductor material in the trenches defining the nanowires; and wherein the fabricating of the side gate comprises etching the dielectric to create a trench for the side gate and depositing the side gate in the trench for the side gate.

High yield substrate assembly. In accordance with a first method embodiment, a plurality of piggyback substrates are attached to a carrier substrate. The edges of the plurality of the piggyback substrates are bonded to one another. The plurality of piggyback substrates are removed from the carrier substrate to form a substrate assembly. The substrate assembly is processed to produce a plurality of integrated circuit devices on the substrate assembly. The processing may use manufacturing equipment designed to process wafers larger than individual instances of the plurality of piggyback substrates.

High germanium percentage (40 atomic percent or greater) silicon germanium (SiGe) graded buffer layers are provided in which stacking fault formation and dislocation defect density are drastically suppressed. Notably, a lattice matched heterogeneous semiconductor material interlayer of Ga(As.sub.1-yP.sub.y) wherein y is from 0 to 1 is formed between each of the SiGe layers of the graded buffer layer to reduce the propagation of threading arm dislocation to the surface and inhibit the formation of stacking faults in each subsequent SiGe layer, and therewith drastically reduce the surface defect density.

High germanium percentage (40 atomic percent or greater) silicon germanium (SiGe) graded buffer layers are provided in which stacking fault formation and dislocation defect density are drastically suppressed. Notably, a lattice matched heterogeneous semiconductor material interlayer of Ga(As.sub.1-yP.sub.y) wherein y is from 0 to 1 is formed between each of the SiGe layers of the graded buffer layer to reduce the propagation of threading arm dislocation to the surface and inhibit the formation of stacking faults in each subsequent SiGe layer, and therewith drastically reduce the surface defect density.

A semiconductor laminate includes a substrate composed of InP, a first buffer layer composed of InP containing less than 110.sup.21 cm.sup.3 Sb and disposed on the substrate, and a second buffer layer composed of InGaAs and disposed on the first buffer layer. The first buffer layer includes a first layer that has a higher concentration of Sb than the substrate and that is arranged to include a first main surface which is a main surface of the first buffer layer on the substrate side. The second buffer layer includes a second layer that has a lower concentration of Sb than the first layer and that is arranged to include a second main surface which is a main surface of the second buffer layer on the first buffer layer side.

A method of producing graphene or other two-dimensional material such as graphene including heating the substrate held within a reaction chamber to a temperature that is within a decomposition range of a precursor, and that allows two-dimensional crystalline material formation from a species released from the decomposed precursor; establishing a steep temperature gradient (preferably >1000 C. per meter) that extends away from the substrate surface towards an inlet for the precursor; and introducing precursor through the relatively cool inlet and across the temperature gradient towards the substrate surface. The steep temperature gradient ensures that the precursor remains substantially cool until it is proximate the substrate surface thus minimizing decomposition or other reaction of the precursor before it is proximate the substrate surface. The separation between the precursor inlet and the substrate is less than 100 mm.

A vapor phase growth device includes a flow channel defining a space through which a source gas for forming an epi layer flows, a susceptor configured to hold a substrate in a state where the substrate faces the space, and a first member disposed vertically above and opposite to the susceptor, the first member having a thermal expansion coefficient not less than 0.7 times and not more than 1.3 times the thermal expansion coefficient of the substrate. The flow channel includes a holding portion configured to hold the first member.