The present disclosure relates to a method of manufacturing a nanowire structure. According to an exemplary process, a substrate is firstly provided. An intact buffer region is formed over the substrate, and a sacrificial top portion of the intact buffer region is eliminated to provide a buffer layer with a planarized top surface. Herein, the planarized top surface has a vertical roughness below 10 Å. Next, a patterned mask with an opening is formed over the buffer layer, such that a portion of the planarized top surface of the buffer layer is exposed. A nanowire is formed over the exposed portion of the planarized top surface of the buffer layer through the opening of the patterned mask. The buffer layer is configured to have a lattice constant that provides a transition between the lattice constant of the substrate and the lattice constant of the nanowire.

Embodiments including apparatus, systems, and methods for nanofabrication are provided. In one example, a method of manufacturing a semiconductor device includes forming a two-dimensional (2D) layer comprising a 2D material on a first substrate and forming a plurality of holes in the 2D layer to create a patterned 2D layer. The method also includes forming a single-crystalline film on the patterned 2D layer and transferring the single-crystalline film onto a second substrate.

Methods, systems, and apparatuses are described for a CMOS compatible substrate having multiple stacks of semiconductor layers. The multiple stacks, at least, each include i) a layer of a tellurium based semiconductor layer on top of ii) a porous silicon layer. The porous silicon layer is a compliant layer to accept structural defects from the tellurium based semiconductor layer into the porous silicon layer. The multiple stacks are grown on the CMOS compatible substrate.

A method for semiconductor film lift-off and substrate transfer is provided. It includes: preparing a semiconductor film-substrate structure including a first substrate layer, multiple seed crystal structures and a semiconductor film layer stacked in that order, and holes are formed among the multiple seed crystal structures and communicated with one another; lifting-off the multiple seed crystal structures and the semiconductor film layer from the first substrate layer; and bonding a side of the multiple seed crystal structures facing away from the semiconductor film layer with a second substrate layer to complete processes of the semiconductor film lifting-off and the substrate transfer. The method can be compatible with various epitaxial substrate materials, and can also retain smooth surface of the device epitaxial layer film without affecting the subsequent process of growing other functional layers for preparing devices on the epitaxial layer film.

In an embodiment a growth structure for a radiation-emitting semiconductor component includes a semiconductor substrate containing a material based on arsenide compound semiconductors and a buffer structure arranged on the semiconductor substrate, wherein the buffer structure includes a buffer layer having at least one n-doped layer and wherein the n-doped layer contains oxygen, and a molar fraction of oxygen in the n-doped layer is between 10.sup.15 cm.sup.−3 and 10.sup.19 cm.sup.−3, inclusive.

A semiconductor device has a substrate and graphene with semiconducting properties or diamond region formed on the substrate. The graphene with semiconducting properties or diamond region is formed on or within the substrate using liquid-phase-epitaxy growth of graphene enabled by a catalytic alloy of Ni and Cu. The substrate can be silicon, silicon carbide, gallium arsenide, gallium nitride, germanium, or indium phosphide. A semiconductor component is formed over the graphene with semiconducting properties or diamond region and substrate. The semiconductor component can be a power MOSFET, IGBT, or CTIGBT with a gate structure formed over the substrate, source region adjacent to the gate structure, and drain region adjacent to the gate structure opposite the source region. The graphene with semiconducting properties or diamond region is formed under a gate of the MOSFET to reduce drain to source resistance, as well as providing radiation hardening for the device.

A method of performing HVPE heteroepitaxy comprises exposing a substrate to a carrier gas, a first precursor gas, a Group II/III element, and ternary-forming gasses (V/VI group precursor), to form a heteroepitaxial growth of a binary, ternary, and/or quaternary compound on the substrate; wherein the carrier gas is H.sub.2, wherein the first precursor gas is HCl, the Group II/III element comprises at least one of Zn, Cd, Hg, Al, Ga, and In; and wherein the ternary-forming gasses comprise at least two or more of AsH.sub.3 (arsine), PH.sub.3 (phosphine), H.sub.2Se (hydrogen selenide), H.sub.2Te (hydrogen telluride), SbH.sub.3 (hydrogen antimonide, or antimony tri-hydride, or stibine), H.sub.2S (hydrogen sulfide), NH.sub.3 (ammonia), and HF (hydrogen fluoride); flowing the carrier gas over the Group II/III element; exposing the substrate to the ternary-forming gasses in a predetermined ratio of first ternary-forming gas to second ternary-forming gas (1tf:2tf ratio); and changing the 1tf:2tf ratio over time.

A method for forming a III-V construction over a group IV substrate comprises providing an assembly comprising the group IV substrate and a dielectric thereon. The dielectric layer comprises a trench exposing the group IV substrate. The method further comprises initiating growth of a first III-V structure in the trench, continuing growth out of the trench on top of the bottom part, growing epitaxially a sacrificial second III-V structure on the top part of the first III-V structure, and growing epitaxially a third III-V structure on the sacrificial second III-V structure. The third III-V structure comprises a top III-V layer. The method further comprises physically disconnecting a first part of the top layer from a second part thereof, and contacting the sacrificial second III-V structure with the liquid etching medium.

Methods, systems, and apparatuses are described for a CMOS compatible substrate having multiple stacks of semiconductor layers. The multiple stacks, at least, each include i) a layer of a tellurium based semiconductor layer on top of ii) a porous silicon layer. The porous silicon layer is a compliant layer to accept structural defects from the tellurium based semiconductor layer into the porous silicon layer. The multiple stacks are grown on the CMOS compatible substrate.

The present invention relates to a novel provided gallium arsenide substrates as well as the use thereof. The gallium arsenide substrates provided according to the invention exhibit a so far not obtained surface quality, in particular a homogeneity of surface properties, which is detectable by means of optical surface analyzers, by way of example by means of ellipsometric lateral substrate mapping for optical contact-free quantitative characterization.