A template-assisted method for the synthesis of 2D nanosheets comprises growing a 2D material on the surface of a nanoparticle substrate that acts as a template for nanosheet growth. The 2D nanosheets may then be released from the template surface, e.g. via chemical intercalation and exfoliation, purified, and the templates may be reused.

A nanowire device includes a first component formed on a substrate and a second component disposed apart from the first component on the substrate. A nanowire is configured to connect the first component to the second component. An anchor pad is formed along a span of the nanowire and configured to support the nanowire along the span to prevent sagging.

Provided is a composite wafer (c-wafer) having an oxide single-crystal film transferred onto a support wafer (s-wafer), the film being a lithium tantalate or lithium niobate film, and c-wafer being unlikely to have cracking or peeling caused in the lamination interface between the film and s-wafer. More specifically, provided is a method of producing c-wafer, including steps of: implanting hydrogen atom ions or molecule ions from a surface of the oxide wafer (o-wafer) to form an ion-implanted layer inside thereof; subjecting at least one of the surface of o-wafer and a surface of s-wafer to surface activation; bonding the surfaces together to obtain a laminate; providing at least one of the surfaces of the laminate with a protection wafer having thermal expansion coefficient smaller than that of o-wafer; and heat-treating the laminate with the protection wafer at 80 C. or higher to split the laminate along the layer to obtain c-wafer.

A method of manufacturing ZnO-containing semiconductor structure includes steps of: (a) forming a subsidiary lamination, including alternately laminating at least two periods of active oxygen layers and ZnO-containing semiconductor layers doped with at least one species of group 3B element; (b) alternately laminating said subsidiary lamination and AgO layer, sandwiching an active oxygen layer, to form lamination structure; and (c) carrying out annealing in atmosphere in which active oxygen exists and pressure is below 10.sup.2 Pa, intermittently irradiating oxygen radical beam on a surface of said lamination structure, forming a p-type ZnO-containing semiconductor structure co-doped with said group 3B element and Ag.

A nanowire device includes a first component formed on a substrate and a second component disposed apart from the first component on the substrate. A nanowire is configured to connect the first component to the second component. An anchor pad is formed along a span of the nanowire and configured to support the nanowire along the span to prevent sagging.

In a method of treating a semiconductor substrate, a plurality of active regions and a plurality of trench isolation regions are formed by selectively etching the semiconductor substrate. The semiconductor substrate is washed by providing deionized water to the semiconductor substrate. A silicon-based solution is provided to the semiconductor substrate by replacing the deionized water disposed on the semiconductor substrate with the silicon-based solution. A silicon oxide material is formed from the silicon-based solution by performing a heat treatment on the silicon-based solution and the semiconductor substrate. The silicon oxide material fills the trench isolation regions.

A transistor includes a multilayer film in which an oxide semiconductor film and an oxide film are stacked, a gate electrode, and a gate insulating film. The multilayer film overlaps with the gate electrode with the gate insulating film interposed therebetween. The multilayer film has a shape having a first angle between a bottom surface of the oxide semiconductor film and a side surface of the oxide semiconductor film and a second angle between a bottom surface of the oxide film and a side surface of the oxide film. The first angle is acute and smaller than the second angle. Further, a semiconductor device including such a transistor is manufactured.

The present disclosure provides a method for fabricating a vertical heterojunction of metal chalcogenides. The method includes steps of providing a multi-layer material, performing an ion implantation and performing an annealing. The multi-layer material has a carrier and a metal layer, in which the metal layer covers the carrier to form an interface. The carrier includes an oxide of a first metal element, and the metal layer includes a second metal element. The step of performing the ion implantation is to inject a chalcogen ion source into the multi-layer material to allow a plurality of chalcogen ions to be implanted in a depth area of the multi-layer material, and the depth area includes the interface. The step of performing the annealing is to form a first metal chalcogenide and a second metal chalcogenide at two sides of the interface, respectively.

A semiconductor device is manufactured using a transistor in which an oxide semiconductor is included in a channel region and variation in electric characteristics due to a short-channel effect is less likely to be caused. The semiconductor device includes an oxide semiconductor film having a pair of oxynitride semiconductor regions including nitrogen and an oxide semiconductor region sandwiched between the pair of oxynitride semiconductor regions, a gate insulating film, and a gate electrode provided over the oxide semiconductor region with the gate insulating film positioned therebetween. Here, the pair of oxynitride semiconductor regions serves as a source region and a drain region of the transistor, and the oxide semiconductor region serves as the channel region of the transistor.

To suppress a change in electrical characteristics and to improve reliability in a semiconductor device using a transistor including an oxide semiconductor. The semiconductor device includes a gate electrode over an insulating surface, an oxide semiconductor film overlapping with the gate electrode, a gate insulating film which is between the gate electrode and the oxide semiconductor film and is in contact with a surface of the oxide semiconductor film, a protective film in contact with an opposite surface of the surface of the oxide semiconductor film, and a pair of electrodes in contact with the oxide semiconductor film. In the gate insulating film or the protective film, the amount of gas having a mass-to-charge ratio m/z of 17 released by heat treatment is greater than the amount of nitrogen oxide released by heat treatment.