The present disclosure provides a semiconductor device structure in accordance with some embodiments. In some embodiments, the semiconductor device structure includes a semiconductor substrate of a first semiconductor material and having first recesses. The semiconductor device structure further includes a first gate stack formed on the semiconductor substrate and being adjacent the first recesses. In some examples, a passivation material layer of a second semiconductor material is formed in the first recesses. In some embodiments, first source and drain (S/D) features of a third semiconductor material are formed in the first recesses and are separated from the semiconductor substrate by the passivation material layer. In some cases, the passivation material layer is free of chlorine.

The invention relates to a process for the preparation of a semiconductor material comprising at least one entirely monocrystalline semiconductor layer, said process comprising the steps of preparation of the surface of a first substrate to receive a monocrystalline silicon layer; deposition by Plasma-Enhanced Chemical Vapor Deposition (PECVD) of a layer of monocrystalline silicon by epitaxial growth with a growth rate gradient on the silicon layer monocrystalline obtained in step (i); and epitaxial growth of a monocrystalline layer of a semiconductor material on the monocrystalline silicon layer obtained in step (ii), to thus obtain a material comprising at least one entirely monocrystalline semiconductor layer. The invention also relates to a multilayer material comprising a monocrystalline layer of semiconductor material.

There is included (a) forming a chlorine-containing semiconductor layer on an insulating film provided on a surface of a substrate by supplying a first gas containing a semiconductor element and chlorine to the substrate; and (b) forming a semiconductor film on the chlorine-containing semiconductor layer by supplying a second gas containing a semiconductor element to the substrate, wherein a chlorine concentration in the chlorine-containing semiconductor layer formed in (a) is made 1.0×10.sup.20 atoms/cm.sup.3 or more and 1.0× 10.sup.22 atoms/cm.sup.3 or less.

Methods, transistors, and systems are discussed related to anisotropically etching back deposited epitaxial source and drain semiconductor materials for reduced lateral source and drain spans in the fabricated transistors. Such lateral width reduction of the source and drain materials enables improved transistor scaling and perturbation reduction in the resultant source and drain semiconductor materials.

A substrate processing method includes: preparing a substrate which includes a base having an epitaxial layer formed by epitaxial growth, and an insulating film formed on the base and having a penetration portion that exposes the epitaxial layer; forming a silicon film on a surface of the epitaxial layer exposed from the penetration portion rather than a side wall of the penetration portion; and forming a metal film on the silicon film formed on the surface of the epitaxial layer rather than the side wall of the penetration portion, and causing the silicon film to react with the metal film to form a metal silicide film.

Embodiments of the invention include a semiconductor device having a fin-shaped channel with a bottom surface, sidewalls and a top surface. A first source or drain (S/D) region is communicatively coupled to the fin-shaped channel, and a sub-channel region is between the bottom surface of the fin-shaped channel and a substrate. A U-shaped dielectric region within a first portion of the sub-channel region, wherein the U-shaped dielectric region includes a bottom isolation layer and a first inner spacer region. A wrap-around gate structure extends around the bottom surface, the sidewalls and the top surface of the fin-shaped channel, wherein a bottom region of the wrap-around gate structure is within a second portion of the sub-channel region.

Methods of reducing wafer bowing in 3D DRAM devices are described using a 3-color process. A plurality of film stacks are formed on a substrate surface, each of the film stacks comprises two doped SiGe layers having different dopant amounts and/or Si:Ge ratios and a doped silicon layer. 3D DRAM devices are also described.

A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an epitaxial layer adjacent to the gate structure, and then forming a first cap layer on the epitaxial layer. Preferably, a top surface of the first cap layer includes a curve concave upward and a bottom surface of the first cap layer includes a planar surface higher than a top surface of the substrate.

Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a doped semiconductor material between source regions and drain regions of the device. The method includes doping semiconductor material layers between source regions and drain regions of an electronic device.

A semiconductor device including a barrier layer surrounding a work function metal layer and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate; a first channel region over the semiconductor substrate; a second channel region over the first channel region; gate dielectric layers surrounding the first channel region and the second channel region; work function metal layers surrounding the gate dielectric layers; and barrier layers surrounding the work function metal layers, a first barrier layer surrounding the first channel region being merged with a second barrier layer surrounding the second channel region.