A method for forming a III-V construction over a group IV substrate comprises providing an assembly comprising the group IV substrate and a dielectric thereon. The dielectric layer comprises a trench exposing the group IV substrate. The method further comprises initiating growth of a first III-V structure in the trench, continuing growth out of the trench on top of the bottom part, growing epitaxially a sacrificial second III-V structure on the top part of the first III-V structure, and growing epitaxially a third III-V structure on the sacrificial second III-V structure. The third III-V structure comprises a top III-V layer. The method further comprises physically disconnecting a first part of the top layer from a second part thereof, and contacting the sacrificial second III-V structure with the liquid etching medium.

A method for preparation of orientation-patterned (OP) templates comprising the steps of: depositing a first layer of a first material on a common substrate by a far-from-equilibrium process; and depositing a first layer of a second material on the first layer of the first material by a close-to-equilibrium process, wherein a first assembly is formed. The first material and the second material may be the same material or different materials. The substrate material may be Al.sub.2O.sub.3 (sapphire), silicon (Si), germanium (Ge), GaAs, GaP, GaSb, InAs, InP, CdTe, CdS, CdSe, or GaSe. The first material deposited on the common substrate may be one or more electronic or optical binary materials from the group consisting of AlN, GaN, GaP, InP, GaAs, InAs, AlAs, ZnSe, GaSe, ZnTe, CdTe, HgTe, GaSb, SiC, CdS, CdSe, or their ternaries or quaternaries. The far-from-equilibrium process is one of MOCVD and MBE, and the close-to-equilibrium process is HVPE.

A second semiconductor layer is oxidized through a groove and a fourth semiconductor layer is oxidized, a first oxide layer is formed, and a second oxide layer is formed. By oxidizing the entire second semiconductor layer and the fourth semiconductor layer, the first oxide layer and the second oxide layer in an amorphous state are formed.

A layered structure comprising a substrate having a first deformation. Also one or more device layers forming a device and having a second deformation. A deformation control layer which is pseudomorphic with respect to the substrate and having a third deformation. The deformation control layer is selected such that a sum of the first, second and third deformations matches a target level of deformation. Advantageously the layered structure has a controlled, known deformation which can be compressive, tensile or zero.

An embodiment includes a III-V material based device, comprising: a first III-V material based buffer layer on a silicon substrate; a second III-V material based buffer layer on the first III-V material based buffer layer, the second III-V material including aluminum; and a III-V material based device channel layer on the second III-V material based buffer layer. Another embodiment includes the above subject matter and the first and second III-V material based buffer layers each have a lattice parameter equal to the III-V material based device channel layer. Other embodiments are included herein.

A semiconductor device includes a substrate comprising a layer made of Ge and a semiconductor multilayer structure grown on the layer made of Ge. The semiconductor multilayer structure includes at least one first layer comprising a material selected from a group consisting of Al.sub.xGa.sub.1-xAs, Al.sub.xGa.sub.1-x-yIn.sub.yAs, Al.sub.xGa.sub.1-x-yIn.sub.yAs.sub.1-zP.sub.z, Al.sub.xGa.sub.1-x-yIn.sub.yAs.sub.1-zN.sub.z, and Al.sub.xGa.sub.1-x-yIn.sub.yAs.sub.1-z-cN.sub.zP.sub.c, Al.sub.xGa.sub.1-x-yIn.sub.yAs.sub.1-z-cN.sub.zSb.sub.c, and Al.sub.xGa.sub.1-x-yIn.sub.yAs.sub.1-z-cP.sub.zSb.sub.c, wherein for any material a sum of the contents of all group-III elements equals 1 and a sum of the contents of all group-V elements equals 1. The semiconductor multilayer structure also includes at least one second layer comprising a material selected from a group consisting of GaInAsNSb, GaInAsN, AlGaInAsNSb, AlGaInAsN, GaAs, GaInAs, GaInAsSb, GaInNSb, GaInP, GaInPNSb, GaInPSb, GaInPN, AlInP, AlInPNSb, AlInPN, AlInPSb, AlGaInP, AlGaInPNSb, AlGaInPN, AlGaInPSb, GaInAsP, GaInAsPNSb, GaInAsPN, GaInAsPSb, GaAsP, GaAsPNSb, GaAsPN, GaAsPSb, AlGaInAs and AlGaAs.

An indium phosphide substrate, a method of inspecting thereof and a method of producing thereof are provided, by which an epitaxial film grown on the substrate is rendered excellently uniform, thereby allowing improvement in PL characteristics and electrical characteristics of an epitaxial wafer formed using this epitaxial film. The indium phosphide substrate has a first main surface and a second main surface, a surface roughness Ra1 at a center position on the first main surface, and surface roughnesses Ra2, Ra3, Ra4, and Ra5 at four positions arranged equidistantly along an outer edge of the first main surface and located at a distance of 5 mm inwardly from the outer edge. An average value m1 of the surface roughnesses Ra1, Ra2, Ra3, Ra4, and Ra5 is 0.5 nm or less, and a standard deviation σ1 of the surface roughnesses Ra1, Ra2, Ra3, Ra4, and Ra5 is 0.2 nm or less.

An integrated circuit die includes a quad-gate device nanowire of channel material for a transistor (e.g., single material or stack to be a channel of a MOS device) formed by removing a portion of a sub-fin material from below the channel material, where the sub-fin material was grown in an aspect ration trapping (ART) trench. In some cases, in the formation of such nanowires, it is possible to remove the defective fin material or area under the channel. Such removal isolates the fin channel, removes the fin defects and leakage paths, and forms the nanowire of channel material having four exposed surfaces upon which gate material may be formed.

Semiconductor devices are provided which comprise III-V FINFET devices that are formed with different semiconductor fin widths to obtain different threshold voltages, as well as methods for fabricating such III-V FINFET devices. For example, a semiconductor device comprises first and second semiconductor fins, which are formed of a III-V compound semiconductor material, and which have a first width W1 and a second width W2, respectively, wherein W1 is less than W2. First and second gate structures of first and second FINFET devices are formed over a portion of the first and second semiconductor fins, respectively. The first FINFET device comprises a first threshold voltage and the second FINFET device comprises a second threshold voltage. The first threshold voltage is greater than the second threshold voltage as a result of the first width W1 being less than the second width W2.

Semiconductor devices including a subfin including a first III-V compound semiconductor and a channel including a second III-V compound semiconductor are described. In some embodiments the semiconductor devices include a substrate including a trench defined by at least two trench sidewalls, wherein the first III-V compound semiconductor is deposited on the substrate within the trench and the second III-V compound semiconductor is epitaxially grown on the first III-V compound semiconductor. In some embodiments, a conduction band offset between the first III-V compound semiconductor and the second III-V compound semiconductor is greater than or equal to about 0.3 electron volts. Methods of making such semiconductor devices and computing devices including such semiconductor devices are also described.