Patent classifications
H01L21/02461
EPITAXIAL GROWTH ON A GALLIUM ARSENIDE PHOSPHIDE CAPPED MATERIAL ON A GALLIUM ARSENIDE SUBSTRATE
A semiconductor device fabrication method in which a growing process is followed by a capping process in which a phosphor containing material cap layer is deposited over a final GaAs based layer. The wafer, containing many such substrates, can be removed from the reaction chamber to continue processing at a later time without creating an oxide layer on the final GaAs based layer. In continuing processing, a decomposition process selectively decomposes the phosphor containing material cap layer, after which a regrowing process is performed to grow additional layers of the device structure. The capping, decomposition and regrowth processes can be repeated multiple times on the semiconductor devices on the wafer during device fabrication.
SINGLE CRYSTAL SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME
A single crystal semiconductor structure includes: an amorphous substrate; a single crystal semiconductor layer provided on the amorphous substrate; and a thin orienting film provided between the amorphous substrate and the single crystal semiconductor layer, wherein the thin orienting film is a single crystal thin film, and the thin orienting film has a non-zero thickness that is equal to or less than 10 times a critical thickness h.sub.c.
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
What is provided here are: a step of forming a first semiconductor layer on a base member; a step of forming a mask on the first semiconductor layer; a step of etching the first semiconductor layer by using the mask, to thereby form a semiconductor structure; a step of forming a second semiconductor layer in a region abutting on a side surface of the semiconductor structure, said second semiconductor layer having a convex portion abutting to the mask; a convex-portion removing step of removing the convex portion by supplying an etching gas thereto; and a regrown-layer forming step of supplying a material gas onto the semiconductor structure and the second semiconductor layer, to thereby form a regrown layer; wherein the convex-portion removing step and the regrown-layer forming step are executed in a same manufacturing apparatus.
OPTICAL DEVICE STRUCTURE AND METHOD FOR MANUFACTURING SAME
On a semiconductor substrate, a first insulation layer having a first opening is formed. Next, on the first insulation layer, a second insulation layer having a second opening that is wider than the first opening is formed. Next, from the surface of the semiconductor substrate at the bottom of the first opening, a semiconductor layer for constituting an optical device is formed through the first opening.
Buffer layers having composite structures
Disclosed is a wafer or a material stack for semiconductor-based optoelectronic or electronic devices that minimizes or reduces misfit dislocation, as well as a method of manufacturing such wafer of material stack. A material stack according to the disclosed technology includes a substrate; a basis buffer layer of a first material disposed above the substrate; and a plurality of composite buffer layers disposed above the basis buffer layer sequentially along a growth direction. The growth direction is from the substrate to a last composite buffer layer of the plurality of composite buffer layers. Each composite buffer layer except the last composite buffer layer includes a first buffer sublayer of the first material, and a second buffer sublayer of a second material disposed above the first buffer sublayer. The thicknesses of the first buffer sublayers of the composite buffer layers decrease along the growth direction.
Semiconductor structure and manufacturing method thereof
The present disclosure provides a semiconductor structure, including a first semiconductor device having a first surface and a second surface, the second surface being opposite to the first surface, a semiconductor substrate over the first surface of the first semiconductor device, and a III-V etch stop layer in contact with the second surface of the first semiconductor device. The present disclosure also provides a manufacturing method of a semiconductor structure, including providing a temporary substrate having a first surface, forming a III-V etch stop layer over the first surface, forming a first semiconductor device over the III-V etch to stop layer, and removing the temporary substrate by an etching operation and exposing a surface of the III-V etch stop layer.
Method for preparing a heterostructure
The present disclosure provides a method for preparing heterostructure, which includes providing a donor substrate and forming a sacrificial layer on a surface of the donor substrate; forming a thin film cover layer on a surface of the sacrificial layer, wherein a top surface of the thin film cover layer is an implantation surface; performing ion implantation from the implantation surface, such that a defect layer is formed in the sacrificial layer; providing an acceptor substrate, and bonding the acceptor substrate to the implantation surface of the thin film cover layer; removing the sacrificial layer along the defect layer. The method for preparing the heterostructure of the present disclosure can successfully transfer the thin film cover layer to the acceptor substrate. The present disclosure can provide a compliant substrate, while the semiconductor donor substrate material can be reused, therefore is energy-efficient and environmental-friendly.
METHOD OF MANUFACTURING SEMICONDUCTOR OPTICAL DEVICE AND INTERMEDIATE ARTICLE OF SEMICONDUCTOR OPTICAL DEVICE
A method of manufacturing a semiconductor optical device of this disclosure includes the steps of forming an etch stop layer on an InP growth substrate, the etch stop layer having a thickness of 100 nm or less; and forming a semiconductor laminate on the etch stop layer by stacking a plurality of InGaAsP-based III-V group compound semiconductor layers containing at least In and P. Further, an intermediate article of a semiconductor optical device of the present disclosure includes an InP growth substrate; an etch stop layer formed on the InP growth substrate, the etch stop layer having a thickness of 100 nm or less; and a semiconductor laminate formed on the etch stop layer, including a plurality of InGaAsP-based III-V group compound semiconductor layers containing at least In and P stacked one another.
Semiconductor structure and manufacturing method thereof
The present disclosure provides a semiconductor structure, including a first semiconductor device having a first surface and a second surface, the second surface being opposite to the first surface, a semiconductor substrate over the first surface of the first semiconductor device, and a III-V etch stop layer in contact with the second surface of the first semiconductor device. The present disclosure also provides a manufacturing method of a semiconductor structure, including providing a temporary substrate having a first surface, forming a III-V etch stop layer over the first surface, forming a first semiconductor device over the etch stop layer, and removing the temporary substrate by an etching operation and exposing a surface of the III-V etch stop layer.
Fabrication of semiconductor substrates
A method for fabricating a semiconductor substrate comprises providing a crystalline base substrate, forming an insulating layer on the crystalline base substrate and forming a trench in the insulating layer. This exposes a seed surface of the base substrate. The trench has sidewalls and a bottom. The bottom corresponds to the seed surface of the base substrate. The method further comprises growing, at a first growth step, an elongated seed structure in the trench from the seed surface of the substrate and forming a cavity structure above the insulating layer. The cavity structure covers the elongated seed structure and extends laterally to the elongated seed structure. The method comprises a further step of growing, at a second growth step, the semiconductor substrate in the cavity structure from the elongated seed structure. The invention is notably also directed to corresponding semiconductor structures and corresponding semiconductor substrates.