The present invention relates to a method for manufacturing a diamond substrate, and more particularly, to a method of growing diamond after forming a structure of an air gap having a crystal correlation with a lower substrate by heat treatment of a photoresist pattern and an air gap forming film material on a substrate such as sapphire (Al.sub.2O.sub.3). Through such a method, a process is simplified and the cost is lowered when large-area/large-diameter single crystal diamond is heterogeneously grown, stress due to differences in a lattice constant and a coefficient of thermal expansion between the heterogeneous substrate and diamond is relieved, and an occurrence of defects or cracks is reduced even when a temperature drops, such that a high-quality single crystal diamond substrate may be manufactured and the diamond substrate may be easily self-separated from the heterogeneous substrate.

Disclosed herein are compositions and methods for making polycrystalline thin films having very large grains sizes and exhibiting improved properties over existing thin films.

A method includes: providing a bottom layer; forming a first transistor over a substrate; forming a bottom electrode over the transistor; depositing a first seed layer over the bottom electrode; performing a surface treatment on the first seed layer, wherein after the surface treatment the first seed layer includes at least one of a tetragonal crystal phase and an orthorhombic crystal phase; depositing a dielectric layer over the bottom layer adjacent to the first seed layer, the dielectric layer including an amorphous crystal phase; depositing an upper layer over the dielectric layer; performing a thermal operation on the dielectric layer to thereby convert the dielectric layer into a ferroelectric layer.

A thin film transistor may be manufactured by forming a gate electrode in an insulating layer over a substrate, forming a gate dielectric over the gate electrode and the insulating layer, forming an active layer over the gate electrode, and forming a source electrode and a drain electrode contacting a respective portion of a top surface of the active layer. A surface oxygen concentration may be increased in at least one of the gate dielectric and the active layer by introducing oxygen atoms into a surface region of a respective one of the gate dielectric and the active layer.

Various forms of Mg.sub.xGe.sub.1-xO.sub.2-x are disclosed, where the MgxGe.sub.1-xO.sub.2-x are epitaxial layers formed on a substrate comprising a substantially single crystal substrate material. The epitaxial layer of Mg.sub.xGe.sub.1-xO.sub.2-x has a crystal symmetry compatible with the substrate material. Semiconductor structures and devices comprising the epitaxial layer of Mg.sub.xGe.sub.1-xO.sub.2-x are disclosed, along with methods of making the epitaxial layers and semiconductor structures and devices.

An electrochemical sensor array includes a thermal oxide configured to interface with one or more analytes. There is a transistor device layer that includes a plurality of field effect transistors (FETs) on top of the thermal oxide. A contact and wiring structure layer is on top of the transistor device layer and operative to couple to control nodes of each of the plurality of FETs. The contact and wiring structure are on a side opposite to that of the thermal oxide.

Various forms of Mg.sub.xGe.sub.1-xO.sub.2-x are disclosed, where the Mg.sub.xGe.sub.1-xO.sub.2-x are epitaxial layers formed on a substrate comprising a substantially single crystal substrate material. The epitaxial layer of Mg.sub.xGe.sub.1-xO.sub.2-x has a crystal symmetry compatible with the substrate material. Semiconductor structures and devices comprising the epitaxial layer of Mg.sub.xGe.sub.1-xO.sub.2-x are disclosed, along with methods of making the epitaxial layers and semiconductor structures and devices.

A semiconductor device with favorable electrical characteristics is provided. A semiconductor device with stable electrical characteristics is provided. A highly reliable display device is provided. A method for fabricating the semiconductor device includes a step of forming a semiconductor layer including a metal oxide; a step of forming, over the semiconductor layer, a first conductive layer and a second conductive layer that are apart from each other over the semiconductor layer; a step of performing plasma treatment using a mixed gas including an oxidizing gas and a reducing gas on a region where the semiconductor layer is exposed; a step of forming a first insulating layer over the semiconductor layer, the first conductive layer, and the second conductive layer; and a step of forming a second insulating layer over the first insulating layer. The first insulating layer is formed by a plasma-enhanced chemical vapor deposition method using a mixed gas including a gas containing silicon, an oxidizing gas, and an ammonia gas. The first insulating layer is formed successively after the plasma treatment without exposure to the air.

Systems and methods for forming semiconductor layers, including oxide-based layers, are disclosed in which a material deposition system has a rotation mechanism that rotates a substrate around a center axis of a substrate deposition plane of the substrate. A material source that supplies a material to the substrate has i) an exit aperture with an exit aperture plane and ii) a predetermined material ejection spatial distribution from the exit aperture plane. The exit aperture is positioned at an orthogonal distance, a lateral distance, and a tilt angle relative to the center axis of the substrate. The system can be configured for either i) minimum values for the orthogonal distance and the lateral distance to achieve a desired layer deposition uniformity using a set tilt angle, or ii) the tilt angle to achieve the desired layer deposition uniformity using a set orthogonal distance and a set lateral distance.

A semiconductor device includes: a p-type region including a super-lattice pseudo mixed crystal region in which a first layer and a second layer are alternately stacked. The first layer includes a gallium oxide based semiconductor. The second layer includes a p type semiconductor made of a material different from the first layer.