Patent classifications
H01L21/02499
Methods of manufacturing semiconductor devices
A method of manufacturing a semiconductor device includes forming a three-dimensional (3D) structure on a substrate, forming an adsorption control layer to cover an upper portion of the 3D structure, and forming a material layer on the adsorption control layer and on a lower portion of the 3D structure that is not covered by the adsorption control layer, wherein a minimum thickness of the material layer on the adsorption control layer is less than a maximum thickness of the material layer on the lower portion of the 3D structure.
Systems and Methods for Fabricating Single-Crystalline Diamond Membranes
A buffer layer is employed to fabricate diamond membranes and allow reuse of diamond substrates. In this approach, diamond membranes are fabricated on the buffer layer, which in turn is disposed on a diamond substrate that is lattice-matched to the diamond membrane. The weak bonding between the buffer layer and the diamond substrate allows ready release of the fabricated diamond membrane. The released diamond membrane is transferred to another substrate to fabricate diamond devices, while the diamond substrate is reused for another fabrication.
METHOD FOR MANUFACTURING A BONDED SOI WAFER
Method for manufacturing a bonded SOI wafer by bonding a bond wafer and base wafer, each composed of a silicon single crystal, via an insulator film, including the steps: depositing a polycrystalline silicon layer on the base wafer bonding surface side, polishing the polycrystalline silicon layer surface, forming the insulator film on the bonding surface of the bond wafer, bonding the polished surface of the base wafer polycrystalline silicon layer and bond wafer via the insulator film; thinning the bonded bond wafer to form an SOI layer; wherein, in the step of depositing the polycrystalline silicon layer, a wafer having a chemically etched surface as base wafer; chemically etched surface is subjected to primary polishing followed by depositing the polycrystalline silicon layer on surface subjected to the primary polishing, and in the step polishing the polycrystalline silicon layer surface, which is subjected to secondary polishing or secondary and finish polishing.
Method of intercalating insulating layer between metal and graphene layer and method of fabricating semiconductor device using the intercalation method
A method includes growing a graphene layer on a metal layer, intercalating a first material between the metal layer and the graphene layer by heating the first material at a first pressure and a first temperature, and intercalating a second material between the metal layer and the graphene layer by heating the second material at a second pressure different from the first pressure and a second temperature different from the first temperature. Accordingly, the first material and the second material are chemically bonded to each other to form an insulating layer, and the insulating layer may be between the metal layer and the graphene layer.
Controlled synthesis and transfer of large area heterostructures made of bilayer and multilayer transition metal dichalocogenides
Embodiments are presented herein that provide a TMD system wherein the first layered material is made of heterobilayers or multilayers with semiconducting direct band gaps. The first layered material may be made of multiple layers of different TMD with different stackings, exhibiting smaller direct and indirect band gaps smaller than monolayer systems of TMD.
TWO-DIMENSIONAL LAYERED MATERIAL QUANTUM WELL JUNCTION DEVICES
A quantum well device includes a first layer of a first two-dimensional material, a second layer of a second two-dimensional material, and a third layer of a third two-dimensional material disposed between the first layer and second layer. The first layer, the second layer, and the third layer are adhered predominantly by van der Waals force.
Semiconductor structure with self-aligned wells and multiple channel materials
Embodiments of the present invention provide a semiconductor structure having a strain relaxed buffer, and method of fabrication. A strain relaxed buffer is disposed on a semiconductor substrate. A silicon region and silicon germanium region are disposed adjacent to each other on the strain relaxed buffer. An additional region of silicon or silicon germanium provides quantum well isolation.
Method for making superlattice structures with reduced defect densities
A method for making a semiconductor device may include forming a superlattice on a substrate comprising a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Moreover, forming at least one of the base semiconductor portions may include overgrowing the at least one base semiconductor portion and etching back the overgrown at least one base semiconductor portion.
METHODS AND SYSTEMS RELATING TO PHOTOCHEMICAL WATER SPLITTING
InGaN offers a route to high efficiency overall water splitting under one-step photo-excitation. Further, the chemical stability of metal-nitrides supports their use as an alternative photocatalyst. However, the efficiency of overall water splitting using InGaN and other visible light responsive photocatalysts has remained extremely low despite prior art work addressing optical absorption through band gap engineering. Within this prior art the detrimental effects of unbalanced charge carrier extraction/collection on the efficiency of the four electron-hole water splitting reaction have remained largely unaddressed. To address this growth processes are presented that allow for controlled adjustment and establishment of the appropriate Fermi level and/or band bending in order to allow the photochemical water splitting to proceed at high rate and high efficiency. Beneficially, establishing such material surface charge properties also reduces photo-corrosion and instability under harsh photocatalysis conditions.
Semiconductor device, superconducting device, and manufacturing method of semiconductor device
A semiconductor device of an embodiment includes a layered substance formed by laminating two-dimensional substances in two or more layers. The layered substance includes at least either one of a p-type region having a first intercalation substance between layers of the layered substance and an n-type region having a second intercalation substance between layers of the layered substance. The layered substance includes a conductive region that is adjacent to at least either one of the p-type region and the n-type region. The conductive region includes neither the first intercalation substance nor the second intercalation substance. A sealing member is formed on the conductive region, or on the conductive region and an end of the layered substance.