H01L21/02499

METHOD OF MANUFACTURING A SEMICONDUCTOR COMPONENT, AND WORKPIECE
20210320006 · 2021-10-14 ·

A method for producing a semiconductor component and workpiece are disclosed. In an embodiment a method includes forming a first semiconductor layer over a growth substrate, wherein a material of the first semiconductor layer is In.sub.x1Al.sub.y1Ga.sub.(1-x1-y1)N, with 0≤xl≤1, 0≤yl≤1, applying a first modification substrate over the first semiconductor layer, wherein a material of the first modification substrate has a thermal expansion coefficient which is different from that of the first semiconductor layer, removing the growth substrate thereby obtaining a first layer stack, heating the first layer stack to a first growth temperature and growing a second semiconductor layer over a growth surface of the first semiconductor layer after heating the first layer stack, wherein due to heating a lattice constant of the first semiconductor layer is adapted to a lattice constant of the second semiconductor layer.

SILICON CARBIDE EPITAXIAL SUBSTRATE AND METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE

A silicon carbide epitaxial substrate includes a silicon carbide single crystal substrate and a silicon carbide layer. In a direction parallel to a central region, a ratio of a standard deviation of a carrier concentration of the silicon carbide layer to an average value of the carrier concentration of the silicon carbide layer is less than 5%. The average value of the carrier concentration is more than or equal to 1×10.sup.14 cm.sup.−3 and less than or equal to 5×10.sup.16 cm.sup.−3. In the direction parallel to the central region, a ratio of a standard deviation of a thickness of the silicon carbide layer to an average value of the thickness of the silicon carbide layer is less than 5%. The central region has an arithmetic mean roughness (Sa) of less than or equal to 1 nm. The central region has a haze of less than or equal to 50.

Epitaxial lift-off process of graphene-based gallium nitride

The present invention discloses an epitaxial lift-off process of graphene-based gallium nitride (GaN), and principally solves the existing problems about complex lift-off technique, high cost, and poor quality of lift-off GaN films. The invention is achieved by: first, growing graphene on a well-polished copper foil by CVD method; then, transferring a plurality of layers of graphene onto a sapphire substrate; next, growing GaN epitaxial layer on the sapphire substrate with a plurality of graphene layers transferred by the metal organic chemical vapor deposition (MOCVD) method; finally, lifting off and transferring the GaN epitaxial layer onto a target substrate with a thermal release tape. With graphene, the present invention relieves the stress generated by the lattice mismatch between substrate and epitaxial layer; moreover, the present invention readily lifts off and transfers the epitaxial layer to the target substrate by means of weak Van der Waals forces between epitaxial layer and graphene.

METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES

A method of manufacturing a semiconductor device includes forming a three-dimensional (3D) structure on a substrate, forming an adsorption control layer to cover an upper portion of the 3D structure, and forming a material layer on the adsorption control layer and on a lower portion of the 3D structure that is not covered by the adsorption control layer, wherein a minimum thickness of the material layer on the adsorption control layer is less than a maximum thickness of the material layer on the lower portion of the 3D structure.

SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE WITH DIFFERENT NON-SEMICONDUCTOR MATERIAL MONOLAYERS
20210265465 · 2021-08-26 ·

A semiconductor device may include a semiconductor substrate, and a superlattice on the semiconductor substrate and including a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A first at least one non-semiconductor monolayer may be constrained within the crystal lattice of a first pair of adjacent base semiconductor portions and comprise a first non-semiconductor material, and a second at least one non-semiconductor monolayer may be constrained within the crystal lattice of a second pair of adjacent base semiconductor portions and comprise a second non-semiconductor material different than the first non-semiconductor material.

SINGULATED SUBSTRATES FOR ELECTRONIC PACKAGING AND OTHER APPLICATIONS IN A ROLL FORMAT
20210125869 · 2021-04-29 ·

Embodiments of the disclosure relate to a method for creating a strip of electronic components. In the method, a ribbon of ceramic substrate is provided. The ceramic substrate defines a thickness of no more than 200 μm between a first outer surface and a second outer surface opposite of the first outer surface. A conductive layer is applied to at least one of the first outer surface or the second outer surface of the ceramic substrate. The ceramic substrate is then singulated into individual slabs, and the individual slabs are laminated to a strip of polymeric carrier. The polymeric carrier has a flexural rigidity less than the flexural rigidity of the ceramic substrate. Additionally, embodiments of a roll of electronic components are provided.

PROCESS FOR THE HETERO-INTEGRATION OF A SEMICONDUCTOR MATERIAL OF INTEREST ON A SILICON SUBSTRATE
20210111022 · 2021-04-15 ·

A process for the hetero-integration of a semiconductor material of interest on a silicon substrate, includes a step of structuring the substrate which comprises a step of producing a growth mask on the surface of the silicon substrate, the growth mask comprising a plurality of masking patterns, two masking patterns being separated by a trench wherein the silicon substrate is exposed; a step of forming a two-dimensional buffer layer made of a 2D material, the buffer layer being free of side bonds on its free surface and being formed selectively on at least one silicon plane of [111] orientation in at least one trench, the step of forming a buffer layer being performed after the structuring step; a step of forming at least one layer of a semiconductor material of interest on the buffer layer. The semiconductor material of interest is preferably a IV-IV, III-V, II-VI semiconductor material and/or a 2D semiconductor material.

Method of forming a semiconductor device using layered etching and repairing of damaged portions

A method of fabricating a semiconductor device includes plasma etching a portion of a plurality of metal dichalcogenide films comprising a compound of a metal and a chalcogen disposed on a substrate by applying a plasma to the plurality of metal dichalcogenide films. After plasma etching, a chalcogen is applied to remaining portions of the plurality of metal dichalcogenide films to repair damage to the remaining portions of the plurality of metal dichalcogenide films from the plasma etching. The chalcogen is S, Se, or Te.

FILM FORMING METHOD AND FILM FORMING APPARATUS
20210098254 · 2021-04-01 ·

There is provided a film forming method including: adsorbing fluorine onto a substrate on which a region in which a nitride film is exposed and a region in which an oxide film is exposed are provided adjacent to each other by supplying a fluorine-containing gas to the substrate, and forming a stepped surface on a side surface of the oxide film by selectively etching the nitride film, among the nitride film and the oxide film, so as to cause a surface of the nitride film to be more deeply recessed than a surface of the oxide film; and after the adsorbing the fluorine onto the substrate and forming the stepped surface, selectively forming a semiconductor film on the nitride film, among the nitride film and the oxide film, by supplying a raw material gas including a semiconductor material to the substrate.

Methods of manufacturing semiconductor devices

A method of manufacturing a semiconductor device includes forming a three-dimensional (3D) structure on a substrate, forming an adsorption control layer to cover an upper portion of the 3D structure, and forming a material layer on the adsorption control layer and on a lower portion of the 3D structure that is not covered by the adsorption control layer, wherein a minimum thickness of the material layer on the adsorption control layer is less than a maximum thickness of the material layer on the lower portion of the 3D structure.