A method for manufacturing a semiconductor device includes supplying a silicon-containing gas to a substrate having a recess formed in a surface of the substrate to deposit a silicon film in the recess, supplying, to the substrate, a first etching gas having a first etching profile in which an amount of etching for an upper portion of the recess in a depth direction and an amount of etching for a lower portion of the recess in the depth direction are different from each other, to etch the silicon film in the recess, supplying, to the substrate, a second etching gas having a second etching profile that is different from the first etching profile of the first etching gas to etch the silicon film in the recess, and additionally depositing the silicon film on the already deposited silicon film etched by the second etching gas.

A tilted nanowire structure is provided which has an increased gate length as compared with a horizontally oriented semiconductor nanowire at the same pitch. Such a structure avoids complexity required for vertical transistors and can be fabricated on a bulk semiconductor substrate without significantly changing/modifying standard transistor fabrication processing.

A transistor device and the manufacturing methods are described. The device includes a gate structure having a gate layer and a ferroelectric layer, source and drain terminals, and a crystalline channel portion. The source and drain terminals are disposed at opposite sides of the gate structure. The crystalline channel portion extends between the source and drain terminals. The source and drain terminals are disposed on the crystalline channel portion and the gate structure is disposed on the crystalline channel portion. The crystalline channel portion includes a first material containing a Group III element and a Group V element, the gate layer includes a second material containing a Group III element and a rare-earth element, and the ferroelectric layer includes a third material containing a Group III element, a rare-earth element and a Group V element.

A III-nitride-based semiconductor device is provided. The III-nitride semiconductor device includes a silicon substrate having a surface with a periodic array of recesses formed therein. A discontinuous insulating layer is formed within each recess of the periodic array of recesses such that a portion of the silicon substrate surface between adjacent recesses is free from coverage of the discontinuous insulating layer. A first epitaxial III-nitride semiconductor layer is formed over the silicon substrate with the periodic array of recesses and discontinuous insulating layer formed thereon. A second III-nitride semiconductor layer is disposed over the first III-nitride semiconductor layer and has a bandgap greater than a bandgap of the first III-nitride semiconductor layer. At least one source and at least one drain are disposed over the second III-nitride semiconductor layer. A gate is also disposed over the second III-nitride semiconductor layer between the source and the drain.

Exemplary methods of semiconductor processing may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include depositing a silicon-containing material on the substrate. Subsequent a first period of time, the methods may include providing a germanium-containing precursor to the processing region of the semiconductor processing chamber. The methods may include thermally reacting the silicon-containing precursor and the germanium-containing precursor at a temperature greater than or about 400° C. The methods may include forming a silicon-and-germanium-containing layer on the substrate.

A single crystal semiconductor structure includes: an amorphous substrate; a single crystal semiconductor layer provided on the amorphous substrate; and a thin orienting film provided between the amorphous substrate and the single crystal semiconductor layer, wherein the thin orienting film is a single crystal thin film, and the thin orienting film has a non-zero thickness that is equal to or less than 10 times a critical thickness h.sub.c.

A nitride semiconductor structure includes a Group III nitride semiconductor portion and a Group II-IV nitride semiconductor portion. The Group III nitride semiconductor portion is single crystalline. The Group III nitride semiconductor portion has a predetermined crystallographic plane. The Group II-IV nitride semiconductor portion is provided on the predetermined crystallographic plane of the Group III nitride semiconductor portion. The Group II-IV nitride semiconductor portion is single crystalline. The Group II-IV nitride semiconductor portion contains a Group II element and a Group IV element. The Group II-IV nitride semiconductor portion forms a heterojunction with the Group III nitride semiconductor portion. The predetermined crystallographic plane is a crystallographic plane other than a (0001) plane.

An epitaxial structure includes a substrate, a nucleation layer on the substrate, a buffer layer on the nucleation layer, and a nitride layer on the buffer layer. The nucleation layer consists of regions in a thickness direction, wherein a chemical composition of the regions is Al.sub.(1-x)In.sub.xN, where 0≤x≤1. A maximum value of the x value in the plurality of regions is the same, a minimum value of the x value in the plurality of regions is the same, and an absolute value of a gradient slope of each of the regions is 0.1%/nm to 50%/nm. A thickness of the nucleation layer is less than a thickness of the buffer layer. A roughness of a surface of the nucleation layer in contact with the buffer layer is greater than a roughness of a surface of the buffer layer in contact with the nitride layer.

A single crystal semiconductor structure includes: an amorphous substrate; a single crystal semiconductor layer provided on the amorphous substrate; and a thin orienting film provided between the amorphous substrate and the single crystal semiconductor layer, wherein the thin orienting film is a single crystal thin film, and the thin orienting film has a non-zero thickness that is equal to or less than 10 times a critical thickness h.sub.c.

Systems and methods are described herein to include an epitaxial metal layer between a rare earth oxide and a semiconductor layer. Systems and methods are described to grow a layered structure, comprising a substrate, a first rare earth oxide layer epitaxially grown over the substrate, a first metal layer epitaxially grown over the rare earth oxide layer, and a first semiconductor layer epitaxially grown over the first metal layer. Specifically, the substrate may include a porous portion, which is usually aligned with the metal layer, with or without a rare earth oxide layer in between.