Patent classifications
H01L21/02505
Stress Management Layer for GaN HEMT
A high electron mobility transistor comprising a nucleation layer having a first lattice constant, a back-barrier layer having a second lattice constant and a stress management layer having a third lattice constant which is larger than both first and second lattice constants. The stress management layer compensates some or all of the stress due to the lattice mismatch between the nucleation layer and back barrier layer so that the resulting structure experiences less bow and warp.
THIN FILM TRANSISTORS HAVING A SPIN-ON 2D CHANNEL MATERIAL
Thin film transistors having a spin-on two-dimensional (2D) channel material are described. In an example, an integrated circuit structure includes a first device layer including a first two-dimensional (2D) material layer above a substrate. The first 2D material layer includes molybdenum, sulfur, sodium and carbon. A second device layer including a second 2D material layer is above the substrate. The second 2D material layer includes tungsten, selenium, sodium and carbon.
Method for producing a nitride compound semiconductor component
A method for producing a nitride compound semiconductor component is disclosed. In an embodiment the method includes providing a growth substrate, growing a nucleation layer of an aluminum-containing nitride compound semiconductor onto the growth substrate, growing a tension layer structure for generating a compressive stress, wherein the tension layer structure comprises at least a first GaN semiconductor layer and a second GaN semiconductor layer, and wherein an Al(Ga)N interlayer for generating the compressive stress is disposed between the first GaN semiconductor layer and the second GaN semiconductor layer and growing a functional semiconductor layer sequence of the nitride compound semiconductor component onto the tension layer structure, wherein a growth of the second GaN semiconductor layer is preceded by a growth of a first 3D AlGaN layer on the Al(Ga)N interlayer in such a way that it has nonplanar structures.
Optimized Heteroepitaxial Growth of Semiconductors
A method of performing heteroepitaxy comprises exposing a substrate to a carrier gas, a first precursor gas, a Group II/III element, and a second precursor gas, to form a heteroepitaxial growth of one of GaAs, AlAs, InAs, GaP, InP, ZnSe, GaSe, CdSe, InSe, ZnTe, CdTe, GaTe, HgTe, GaSb, InSb, AlSb, CdS, GaN, and AlN on the substrate; wherein the substrate comprises one of GaAs, AlAs, InAs, GaP, InP, ZnSe, GaSe, CdSe, InSe, ZnTe, CdTe, GaTe, HgTe, GaSb, InSb, AlSb, CdS, GaN, and AlN; wherein the carrier gas is Hz, wherein the first precursor is HCl, the Group II/III element comprises at least one of Zn, Cd, Hg, Al, Ga, and In; and wherein the second precursor is one of AsH.sub.3 (arsine), PH.sub.3 (phosphine), H.sub.2Se (hydrogen selenide), H.sub.2Te (hydrogen telluride), SbH.sub.3 (hydrogen antimonide), H.sub.2S (hydrogen sulfide), and NH.sub.3 (ammonia). The process may be an HVPE (hydride vapor phase epitaxy) process.
Film forming method and crystalline multilayer structure
The disclosure provides a film forming method that enables to obtain an epitaxial film with reduced defects such as dislocations due to a reduced facet growth industrially advantageously, even if the epitaxial film has a corundum structure. When forming an epitaxial film on a crystal-growth surface of a corundum-structured crystal substrate directly or via another layer, using the crystal substrate having an uneven portion on the crystal-growth surface of the crystal substrate, generating and floating atomized droplets by atomizing a raw material solution including a metal; carrying the floated atomized droplets onto a surface of the crystal substrate by using a carrier gas; and causing a thermal reaction of the atomized droplets in a condition of a supply rate limiting state.
Method of manufacturing a semiconductor device and a semiconductor device
In a method of manufacturing a semiconductor device, first and second fin structures are formed over a substrate, an isolation insulating layer is formed over the substrate, a gate structure is formed over channel regions of the first and second fin structures, source/drain regions of the first and second fin structure are recessed, and an epitaxial source/drain structure is formed over the recessed first and second fin structures. The epitaxial source/drain structure is a merged structure having a merger point, and a height of a bottom of the merger point from an upper surface of the isolation insulating layer is 50% or more of a height of the channel regions of the first and second fin structures from the upper surface of the isolation insulating layer.
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREFOR
Disclosed are a semiconductor structure and a manufacturing method therefor, solving a problem that a surface of an epitaxial layer is not easy to flatten as the epitaxial layer has a large stress. The semiconductor structure includes: a substrate; a patterned AlN/AlGaN seed layer on the substrate; and an AlGaN epitaxial layer formed on the patterned AlN/AlGaN seed layer.
NITRIDE SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING NITRIDE SEMICONDUCTOR DEVICE
A nitride semiconductor device includes: a diamond substrate; a first graphene layer provided on the diamond substrate; a second graphene layer provided on the first graphene layer; a nitride semiconductor layer provided on the second graphene layer; and a nitride semiconductor element having an electrode provided on the nitride semiconductor layer, wherein the first and second graphene layers are provided as an interface layer between the diamond substrate and the nitride semiconductor layer.
SILICON CARBIDE SUBSTRATE AND METHOD OF MANUFACTURING THE SAME
In a silicon carbide substrate including: a SiC substrate; and a first semiconductor layer, a second semiconductor layer and a drift layer that are epitaxial layers sequentially formed on the SiC substrate, an impurity concentration of the first semiconductor layer is lower than impurity concentrations of the SiC substrate and the second semiconductor layer, and the second semiconductor layer is formed to have a high impurity concentration or a large thickness.
SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS
A substrate processing method includes: a carry-in step of carrying a substrate having a silicon-containing film on a surface of the substrate into a processing container; a first step of forming an adsorption layer by supplying an oxygen-containing gas into the processing container and causing the oxygen-containing gas to be adsorbed on a surface of the silicon-containing film; a second step of forming a silicon oxide layer by supplying an argon-containing gas into the processing container and causing the adsorption layer and the surface of the silicon-containing film to react with each other with plasma of the argon-containing gas; and a third step of forming a graphene film on the silicon oxide layer by supplying a carbon-containing gas into the processing container with plasma of the carbon-containing gas.