Epitaxial growth of materials, and related systems and articles, are generally described.

A metal oxide thin film transistor is provided and includes a gate, a gate insulating layer, an active layer and a source-drain metal layer stacked on a side of a backplane, the active layer and the gate are provided on both sides of the gate insulating layer, the source-drain metal layer is provided on a side of the active layer away from the backplane, the active layer includes: a first metal oxide semiconductor layer provided on a side of the gate insulating layer away from the gate; a second metal oxide semiconductor layer provided on a surface of the first metal oxide semiconductor layer away from the gate.

In a described example, an integrated circuit (IC) is disclosed that includes a transistor. The transistor includes a substrate, and a buffer structure overlying the substrate. The buffer structure has a first buffer layer, a second buffer layer overlying the first buffer layer, and a third buffer layer overlying the second buffer layer. The first buffer layer has a first carbon concentration, the second buffer layer has a second carbon concentration lower than the first carbon concentration, and the third buffer layer has a third carbon concentration higher than the second carbon concentration. An active structure overlies the buffer structure.

Semiconductor devices and methods of manufacture are provided whereby fences are formed over a substrate and III-V materials are grown over the substrate, wherein the fences block growth of the III-V materials. As such, smaller areas of the III-V materials are grown, thereby preventing stresses that occur with the growth of larger sheets.

A semiconductor device include a substrate, a buffer layer formed on the substrate, a channel layer formed by an intrinsic polycrystalline silicon layer on the buffer layer, polycrystalline source and drain by non-intrinsic silicon formed on both sides of the polycrystalline silicon layer, a source electrode and a drain electrode formed on the polycrystalline source and the drain, a gate electrode corresponding to the channel layer, and an NiSi.sub.2 contact layer located between the source and the source electrode and between the drain and the drain electrode.

According to one embodiment, a wafer includes a substrate and a crystal layer. The substrate includes a plurality of SiC regions including SiC and an inter-SiC region including Si provided between the SiC regions. The crystal layer includes a first layer, and a first intermediate layer provided between the substrate and the first layer in a first direction. The first layer includes SiC and nitrogen. The first intermediate layer includes SiC and nitrogen. A second concentration of nitrogen in the first intermediate layer is higher than a first concentration of nitrogen in the first layer.

A method for manufacturing an III-nitride semiconductor structure is provided. The method includes providing a substrate comprising a first layer having an upper surface of monocrystalline III-nitride material; providing, over the upper surface, a patterned dielectric layer comprising a first dielectric feature; loading the substrate into a process chamber; exposing the substrate to a first gas mixture comprising at least one Group III-metal organic precursor gas, a nitrogen containing gas and hydrogen gas at a predetermined temperature, thereby forming, on the upper surface, a second layer of a monocrystalline III-nitride material by area selective growth wherein two opposing sidewalls of the dielectric feature are oriented parallel to one of the {11-20} crystal planes of the first layer such that upon formation of the second layer of the monocrystalline III-nitride material, a first trench having tapered sidewalls is formed so that the crystal plane of the second layer parallel to the tapered sidewalls is one of the {1-101} crystal planes.

A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.

Hydride phase vapor epitaxy (HVPE) growth apparatus, methods and materials and structures grown thereby. An HVPE reactor includes generation, accumulation, and growth zones. A source material for growth of indium nitride is generated and collected inside the reactor. A first reactive gas reacts with an indium source inside the generation zone to produce a first gas product having an indium-containing compound. The first gas product is cooled and condenses into a liquid or solid condensate or source material having an indium-containing compound. The source material is collected in the accumulation zone. Vapor or gas resulting from evaporation of the condensate forms a second gas product, which reacts with a second reactive gas in the growth zone for growth of indium nitride.

A semiconductor device includes a substrate, a nucleation layer, a buffer layer, first and second nitride-based semiconductor layers, a pair of S/D electrodes, and a gate electrode. The nucleation layer is disposed on the substrate. The buffer layer includes a III-V compound which includes a first element. The buffer layer is disposed on the nucleation layer. The buffer layer has a variable concentration of the first element that decrementally decreases and then incrementally increases as a function of a distance within a thickness of the buffer layer. The first nitride-based semiconductor layer is disposed on the buffer layer. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer. The S/D electrodes and a gate electrode are disposed over the second nitride-based semiconductor layer.