Embodiments of the present invention provide a semiconductor device capable of improving both the thermal stability and contact resistance and a method for fabricating the same. According to an embodiment of the present invention, a semiconductor device may comprise: a contact plug over a substrate, wherein the contact plug includes: a silicide layer having a varying carbon content in a film, and a metal material layer over the silicide layer.

An epitaxial structure includes a substrate, a nucleation layer on the substrate, a buffer layer on the nucleation layer, and a nitride layer on the buffer layer. The nucleation layer consists of regions in a thickness direction, wherein a chemical composition of the regions is Al.sub.(1-x)In.sub.xN, where 0≤x≤1. A maximum value of the x value in the plurality of regions is the same, a minimum value of the x value in the plurality of regions is the same, and an absolute value of a gradient slope of each of the regions is 0.1%/nm to 50%/nm. A thickness of the nucleation layer is less than a thickness of the buffer layer. A roughness of a surface of the nucleation layer in contact with the buffer layer is greater than a roughness of a surface of the buffer layer in contact with the nitride layer.

One or more semiconductor structures comprising a hole draining structure are provided. A semiconductor structure has a first layer formed over a substrate. The first layer has a first concentration of a metal material. The semiconductor structure has a second layer formed over the first layer. The second layer has a second concentration of the metal material different than the first concentration of the metal material. The semiconductor structure has a hole draining structure formed from a superlattice formed between the first layer and the second layer. The hole draining structure has a concentration of the metal material increasing towards the first layer and decreasing towards the second layer.

A high electron mobility transistor comprising a nucleation layer having a first lattice constant, a back-barrier layer having a second lattice constant and a stress management layer having a third lattice constant which is larger than both first and second lattice constants. The stress management layer compensates some or all of the stress due to the lattice mismatch between the nucleation layer and back barrier layer so that the resulting structure experiences less bow and warp.

A III-nitride-based semiconductor wafer is provided that includes a substrate with a central region and a peripheral edge region. One or more intermediate layers may be optionally provided selected from a buffer layer, a seed layer, or a transition layer. A peripheral edge feature is formed in or on a peripheral edge region of the substrate or the transition layer, with one or more peripheral edge passivation layers or peripheral edge surface texturing. The peripheral edge feature extends only around the peripheral edge and not in the central region. One or more III-nitride-based layers is positioned over the central region. In the central region, the III-nitride layer is an epitaxial layer while in the peripheral edge region, it is a polycrystalline layer. Stress due to lattice mismatches and differences in the coefficient of thermal expansion between the III-nitride layer and the substrate is relieved, minimizing defects.

The present disclosure provides a radio frequency device, a silicon carbide homoepitaxial substrate and a manufacturing method thereof. The manufacturing method of the silicon carbide homoepitaxial substrate includes: providing an N-type silicon carbide substrate, forming first grooves in the N-type silicon carbide substrate; forming a defect repair layer on inner walls of the first grooves and outside the first grooves, and forming second grooves in the defect repair layer corresponding to the first grooves; forming an unintentionally doped silicon carbide layer on the defect repair layer, where the second grooves are fully filled with the unintentionally doped silicon carbide layer.

Semiconductor devices and methods of manufacture are provided whereby fences are formed over a substrate and III-V materials are grown over the substrate, wherein the fences block growth of the III-V materials. As such, smaller areas of the III-V materials are grown, thereby preventing stresses that occur with the growth of larger sheets.

A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.

A high electron mobility transistor (HEMT) includes a substrate; and a first semiconductor layer over the substrate. The HEMT further includes a second semiconductor layer over the first semiconductor layer, wherein the second semiconductor layer has a band gap discontinuity with the first semiconductor layer, and at least one of the first semiconductor layer or the second semiconductor layer comprises indium. The HEMT further includes a top layer over the second semiconductor layer. The HEMT further includes a gate electrode over the top layer. The HEMT further includes a source and a drain on opposite sides of the gate electrode, wherein the top layer extends continuously from below the source, below the gate electrode, and to below the drain.

Semiconductor structures and methods for forming those semiconductor structures are disclosed. For example, a semiconductor structure with a p-type superlattice region, an i-type superlattice region, and an n-type superlattice region is disclosed. The semiconductor structure can have a polar crystal structure with a growth axis that is substantially parallel to a spontaneous polarization axis of the polar crystal structure. In some cases, there are no abrupt changes in polarisation at interfaces between each region. At least one of the p-type superlattice region, the i-type superlattice region and the n-type superlattice region can comprise a plurality of unit cells exhibiting a monotonic change in composition from a wider band gap (WBG) material to a narrower band gap (NBG) material or from a NBG material to a WBG material along the growth axis to induce p-type or n-type conductivity.