H01L21/0251

ADVANCED ELECTRONIC DEVICE STRUCTURES USING SEMICONDUCTOR STRUCTURES AND SUPERLATTICES

Semiconductor structures and methods for forming those semiconductor structures are disclosed. For example, a semiconductor structure with a p-type superlattice region, an i-type superlattice region, and an n-type superlattice region is disclosed. The semiconductor structure can have a polar crystal structure with a growth axis that is substantially parallel to a spontaneous polarization axis of the polar crystal structure. In some cases, there are no abrupt changes in polarisation at interfaces between each region. At least one of the p-type superlattice region, the i-type superlattice region and the n-type superlattice region can comprise a plurality of unit cells exhibiting a monotonic change in composition from a wider band gap (WBG) material to a narrower band gap (NBG) material or from a NBG material to a WBG material along the growth axis to induce p-type or n-type conductivity.

GRADED BUFFER LAYERS WITH LATTICE MATCHED EPITAXIAL OXIDE INTERLAYERS
20170288024 · 2017-10-05 ·

A lattice matched epitaxial oxide interlayer is disposed between each semiconductor layer of a graded buffer layer material stack. Each lattice matched epitaxial oxide interlayer inhibits propagation of threading dislocations from one semiconductor layer of the graded buffer layer material stack into an overlying semiconductor layer of the graded buffer layer material stack. This allows for decreasing the thickness of each semiconductor layer within the graded buffer layer material stack. The topmost semiconductor layer of the graded buffer layer material stack, which is a relaxed layer, contains a lower defect density than the other semiconductor layers of the graded buffer layer material stack.

METHOD FOR MANUFACTURING ALUMINUM NITRIDE-BASED TRANSISTOR
20220051888 · 2022-02-17 ·

The present invention relates to a method of manufacturing an AlN-based transistor. An AlN-based high electron mobility transistor (HEMT) element according to the present invention may use an AlN buffer layer, and include an AlGaN composition change layer inserted into a GaN/AlN interface to remove or suppress a degree of generation of a two-dimensional hole gas (2DHG), thereby decreasing an influence of a coulomb drag on a two-dimensional electron gas (2DEG) layer and improving mobility of a two-dimensional electron gas (2DEG).

Semiconductor substrate with stress relief regions

A crystalline base substrate including a first semiconductor material and having a main surface is provided. The base substrate is processed so as to damage a lattice structure of the base substrate in a first region that extends to the main surface without damaging a lattice structure of the base substrate in second regions that are adjacent to the first region. A first semiconductor layer of a second semiconductor material is formed on a portion of the main surface that includes the first and second regions. A third region of the first semiconductor layer covers the first region of the base substrate, and a fourth region of the first semiconductor layer covers the second region of the base substrate. The third region has a crystalline structure that is disorganized relative to a crystalline structure of the fourth region. The first and second semiconductor materials have different coefficients of thermal expansion.

Method of producing epitaxial silicon wafer, epitaxial silicon wafer, and method of producing solid-state imaging device
11245014 · 2022-02-08 · ·

Provided is a method of producing an epitaxial silicon wafer having high gettering capability resulting in even more reduced white spot defects in a back-illuminated solid-state imaging device. The method includes: a first step of irradiating a surface of a silicon wafer with cluster ions of C.sub.nH.sub.m (n=1 or 2, m=1, 2, 3, 4, or 5) generated using a Bernas ion source or an IHC ion source, thereby forming, in the silicon wafer, a modifying layer containing, as a solid solution, carbon and hydrogen that are constituent elements of the cluster ions; and a subsequent second step of forming a silicon epitaxial layer on the surface. In the first step, peaks of concentration profiles of carbon and hydrogen in the depth direction of the modifying layer are made to lie in a range of more than 150 nm and 2000 nm or less from the surface.

MACHINE AND PROCESS FOR CONTINUOUS, SEQUENTIAL, DEPOSITION OF SEMICONDUCTOR SOLAR ABSORBERS HAVING VARIABLE SEMICONDUCTOR COMPOSITION DEPOSITED IN MULTIPLE SUBLAYERS

A system for manufacture of I-III-VI-absorber photovoltaic cells involves sequential deposition of films comprising one or more of silver and copper, with one or more of aluminum indium and gallium, and one or more of sulfur, selenium, and tellurium, as compounds in multiple thin sublayers to form a composite absorber layer. In an embodiment, the method is adapted to roll-to-roll processing of photovoltaic cells. In an embodiment, the method is adapted to preparation of a CIGS absorber layer having graded composition through the layer of substitutions such as tellurium near the base contact and silver near the heterojunction partner layer, or through gradations in indium and gallium content. In a particular embodiment, the graded composition is enriched in gallium at a base of the layer, and silver at the top of the layer. In an embodiment, each sublayer is deposited by co-evaporation of copper, indium, gallium, and selenium, which react in-situ to form CIGS. In a particular embodiment, a special selenium or tellurium source, valve and delivery subsystem is made of quartz, graphite, coated graphite, or molybdenum. In a particular embodiment, an ion-beam source module configured for surface smoothing the solar absorber sublayer surface before passing through the final deposition zone.

SEMICONDUCTOR DEVICE WITH STRAIN RELAXED LAYER

A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.

Super-Flexible Transparent Semiconductor Film and Preparation Method Thereof
20220310384 · 2022-09-29 ·

The present invention discloses a super-flexible transparent semiconductor film and a preparation method thereof, the method includes: providing an epitaxial substrate; growing a sacrificial layer on the epitaxial substrate; stacking and growing at least one layer of Al.sub.1-nGa.sub.nN epitaxial layer on the sacrificial layer, wherein 0<n≤1; growing a nanopillar array containing GaN materials on the Al.sub.1-nGa.sub.nN epitaxial layer; etching the sacrificial layer so as to peel off an epitaxial structure on the sacrificial layer as a whole; and transferring the epitaxial structure after peeling onto a surface of the flexible transparent substrate. Compared to traditional planar films, the present invention can not only improve the crystal quality by releasing stress, but also improve flexibility and transparency through characteristics of the nanopillar materials. In addition, a total thickness of the buffer layer and the sacrificial layer required by the epitaxial structure can be small, and there is no need for additional catalyst during an epitaxial growth process, which is beneficial for reducing epitaxial costs and process difficulty. The present invention is practical in use, and can provide technical support for invisible semiconductor devices and super-flexible devices.

SEMICONDUCTOR STRUCTURE COMPRISING AN ACTIVE SEMICONDUCTOR LAYER OF THE III-V TYPE ON A BUFFER LAYER STACK AND METHOD FOR PRODUCING SEMICONDUCTOR STRUCTURE
20170229549 · 2017-08-10 ·

A semiconductor structure includes a buffer layer stack comprising a plurality of III-V material layers, and the buffer layer stack includes at least one layered substructure. Each layered substructure comprises a compressive stress inducing structure between a respective first buffer layer and a respective second buffer layer positioned higher in the buffer layer stack than the respective first buffer layer. A lower surface of the respective second buffer layer has a lower Al content than an upper surface of the respective first buffer layer. An active semiconductor layer of the III-V type is provided on the buffer layer stack. The surface of the respective relaxation layers is sufficiently rough to inhibit the relaxation of the respective second buffer layer, and comprises a Root Mean Square (RMS) roughness larger than 1 nm. A method is provided for producing the semiconductor structure.

Epitaxial structure and semiconductor device

An epitaxial structure and a semiconductor device are provided in which the epitaxial structure includes at least a SiC substrate, a nucleation layer, and a GaN layer. The nucleation layer is formed on the SiC substrate. The material of the nucleation layer is aluminum gallium nitride doped with a dopant, the Al content in the nucleation layer changes from high to low in the thickness direction, the lattice constant of the nucleation layer is between 3.08 Å and 3.21 Å, and the doping concentration of the nucleation layer changes from high to low in the thickness direction. The GaN layer is formed on the nucleation layer.