Embodiments of the present invention provide a semiconductor device capable of improving both the thermal stability and contact resistance and a method for fabricating the same. According to an embodiment of the present invention, a semiconductor device may comprise: a contact plug over a substrate, wherein the contact plug includes: a silicide layer having a varying carbon content in a film, and a metal material layer over the silicide layer.

A type, size, and location of a crystal defect of an epitaxial layer of a semiconductor wafer containing silicon carbide are detected from a PL image by crystal defect inspection equipment. Detected crystal defects include a triangular polymorph stacking fault generated in the epitaxial layer during epitaxial growth and high-density BPDs extending from the stacking fault and present bundled between the stacking fault and a perfect crystal. Next, a chip region free of the triangular polymorph stacking fault and free of the high-density BPD in a specified area that is in the termination region and is located closer to a chip center than is a specified position is identified as a conforming product. A semiconductor chip set as a conforming product may contain high-density BPDs outside the specified area.

A method of manufacturing a silicon carbide semiconductor device. The method includes providing a starting substrate containing silicon carbide, epitaxially growing an epitaxial layer on the starting substrate to thereby form a semiconductor wafer, forming a plurality of scribe lines at a surface of the semiconductor wafer to delineate a plurality of chip regions, forming a mark in the epitaxial layer, the mark being formed in a marking region that is outside the scribe lines, inspecting the epitaxial layer for a crystal defect, forming a device element structure in at least one of the plurality of chip regions, dicing the semiconductor wafer into a plurality of individual semiconductor chips along the plurality of scribe lines, and identifying, as a conforming product candidate, one of the plurality of semiconductor chips that is free of the crystal defect detected during the inspecting.

The present disclosure is directed to semiconductor structures with source/drain epitaxial stacks having a low-melting point top layer and a high-melting point bottom layer. For example, a semiconductor structure includes a gate structure disposed on a fin and a recess formed in a portion of the fin not covered by the gate structure. Further, the semiconductor structure includes a source/drain epitaxial stack disposed in the recess, where the source/drain epitaxial stack has bottom layer and a top layer with a higher activated dopant concentration than the bottom layer.

The present invention addresses the issue of providing: an SiC substrate having a dislocation conversion layer that can reduce resistance; and a novel technology pertaining to SiC semiconductors. This SiC substrate and SiC semiconductor device comprise a dislocation conversion layer 12 having a doping concentration of at least 1×10.sup.15 cm.sup.−3. As a result of comprising a dislocation conversion layer 12 having this kind of doping concentration: expansion of basal plane dislocations and the occurrence of high-resistance stacking faults can be suppressed; and resistance when SiC semiconductor devices are produced can be reduced.

The present disclosure provides a semiconductor device structure in accordance with some embodiments. In some embodiments, the semiconductor device structure includes a semiconductor substrate of a first semiconductor material and having first recesses. The semiconductor device structure further includes a first gate stack formed on the semiconductor substrate and being adjacent the first recesses. In some examples, a passivation material layer of a second semiconductor material is formed in the first recesses. In some embodiments, first source and drain (S/D) features of a third semiconductor material are formed in the first recesses and are separated from the semiconductor substrate by the passivation material layer. In some cases, the passivation material layer is free of chlorine.

A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.

For the manufacturing of a vertical conduction silicon carbide electronic device, a work wafer, which has a silicon carbide substrate having a work face, is processed. A rough face is formed from the work face of the silicon carbide substrate. The rough face has a roughness higher than a threshold. A metal layer is deposited on the rough face and the metal layer is annealed, thereby causing the metal layer to react with the silicon carbide substrate, forming a silicide layer having a plurality of protrusions of silicide.

An n.sup.--type drift layer is an n.sup.--type epitaxial layer doped with nitrogen as an n-type dopant and is co-doped with aluminum as a p-type dopant, the n.sup.--type drift layer containing the nitrogen and aluminum substantially uniformly throughout. An n-type impurity concentration of the n.sup.--type drift layer is an impurity concentration determined by subtracting the aluminum concentration from the nitrogen concentration of the n.sup.--type drift layer; a predetermined blocking voltage is realized by the impurity concentration. A combined impurity concentration of the nitrogen and aluminum of the n.sup.--type drift layer is at least 3×10.sup.16/cm.sup.3.

Organosilicon chemistry, polymer derived ceramic materials, and methods. Such materials and methods for making polysilocarb (SiOC) and Silicon Carbide (SiC) materials having 3-nines, 4-nines, 6-nines and greater purity. Processes and articles utilizing such high purity SiOC and SiC.