Patent classifications
H01L21/02535
SEMICONDUCTOR COMPOSITE LAYERS
A semiconductor composite layer can include a source electrode and a drain electrode individually comprising both a carrier mobility contributor and an amorphous phase stabilizer. The semiconductor composite layer can further include a semiconductive portion disposed between the source electrode and the drain electrode wherein the semiconductive portion comprises the carrier mobility contributor and the amorphous phase stabilizer, the semiconductivity controller comprising oxygen and an element having an electrode potential that is lower than that of both the carrier mobility contributor and the amorphous phase stabilizer.
Method for forming semiconductor device having boron-doped germanium tin epitaxy structure
A method includes forming a first semiconductor layer over a substrate; forming a second semiconductor layer over the first semiconductor layer; forming a dummy gate structure over the second semiconductor layer; performing an etching process to form a recess in the first and second semiconductor layers; forming a epitaxy structure over in the recess, wherein the epitaxy structure is in contact with the first and second semiconductor layers; performing a solid phase diffusion process to form a doped region in the epitaxy structure, in which the doped region is in contact with the second semiconductor layer and is separated from the first semiconductor layer; and replacing the dummy gate structure with a metal gate structure.
Method for depositing a group IV semiconductor and related semiconductor device structures
A method for depositing a Group IV semiconductor is disclosed. The method may include, providing a substrate within a reaction chamber and heating the substrate to a deposition temperature. The methods may further include, exposing the substrate to at least one Group IV precursor and exposing the substrate to at least one Group IIIA metalorganic dopant precursor. The methods may further include depositing a Group IV semiconductor on a surface of the substrate. Semiconductor device structures including a Group IV semiconductor deposited by the methods of the disclosure are also provided.
TIN OXIDE AND TIN CARBIDE MATERIALS FOR SEMICONDUCTOR PATTERNING APPLICATIONS
A method and apparatus for patterning semiconductor materials using tin-based materials as mandrels, hardmasks, and liner materials are provided. One or more implementations of the present disclosure use tin-oxide and/or tin-carbide materials as hardmask materials, mandrel materials, and/or liner material during various patterning applications. Tin-oxide or tin-carbide materials are easy to strip relative to other high selectivity materials like metal oxides (e.g., TiO.sub.2, ZrO.sub.2, HfO.sub.2, Al.sub.2O.sub.3) to avoid influencing critical dimensions and generate defects. In addition, tin-oxide and tin-carbide have low refractive index, k-value, and are transparent under 663-nm for lithography overlay.
Tin oxide mandrels in patterning
Tin oxide films are used as mandrels in semiconductor device manufacturing. In one implementation the process starts by providing a substrate having a plurality of protruding tin oxide features (mandrels) residing on an exposed etch stop layer. Next, a conformal layer of spacer material is formed both on the horizontal surfaces and on the sidewalls of the mandrels. The spacer material is then removed from the horizontal surfaces exposing the tin oxide material of the mandrels, without fully removing the spacer material residing at the sidewalls of the mandrel (e.g., leaving at least 50%, such as at least 90% of initial height at the sidewall). Next, mandrels are selectively removed (e.g., using hydrogen-based etch chemistry), while leaving the spacer material that resided at the sidewalls of the mandrels. The resulting spacers can be used for patterning the etch stop layer and underlying layers.
APPARATUS, SYSTEMS, AND METHODS OF USING ATOMIC HYDROGEN RADICALS WITH SELECTIVE EPITAXIAL DEPOSITION
Aspects of the present disclosure relate to apparatus, systems, and methods of using atomic hydrogen radicals with epitaxial deposition. In one aspect, nodular defects (e.g., nodules) are removed from epitaxial layers of substrate. In one implementation, a method of processing substrates includes selectively growing an epitaxial layer on one or more crystalline surfaces of a substrate. The epitaxial layer includes silicon. The method also includes etching the substrate to remove a plurality of nodules from one or more non-crystalline surfaces of the substrate. The etching includes exposing the substrate to atomic hydrogen radicals. The method also includes thermally annealing the epitaxial layer to an anneal temperature that is 600 degrees Celsius or higher.
GATE-ALL-AROUND DEVICE
A device comprises a plurality of nanosheets, source/drain stressors, and a gate structure wrapping around the nanosheets. The nanosheets extend in a first direction above a semiconductor substrate and are arranged in a second direction substantially perpendicular to the first direction. The source/drain stressors are on either side of the nanosheets. Each of the source/drain stressors comprises a first epitaxial layer and a second epitaxial layer over the first epitaxial layer. The first and second epitaxial layers are made of a Group IV element and a Group V element. An atomic ratio of the Group V element to the Group IV element in the second epitaxial layer is greater than an atomic ratio of the Group V element to the Group IV element in the first epitaxial layer.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF
A semiconductor device includes a fin extending along a first direction over a substrate, and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate electrode structure, and a stressor layer is between the source/drain region and the semiconductor substrate. The stressor layer includes GeSn or SiGeSn containing 10.sup.19 atoms cm.sup.−3 or less of a dopant, and a portion of the fin under the gate structure is a channel region.
METHOD FOR PRODUCING DOPING RAW-MATERIAL SOLUTION FOR FILM FORMATION, METHOD FOR PRODUCING LAMINATE, DOPING RAW-MATERIAL SOLUTION FOR FILM FORMATION, AND SEMICONDUCTOR FILM
A method for producing a doping raw-material solution for film formation includes a step of firstly mixing a solute including a halogen-containing organic dopant compound or a dopant halide with a first solvent, but not with other solvents to prepare a dopant precursor solution separately from a film-forming raw material, where an acidic solvent is used as the first solvent. A method for producing a doping raw-material solution for film formation enables stable formation of a high-quality thin film having excellent electric characteristics.
METHODS OF FORMING SILICON GERMANIUM STRUCTURES
Methods for forming structures that include forming a heteroepitaxial layer on a substrate are disclosed. The presently disclosed methods comprise epitaxially forming a buffer layer on the substrate. The substrate has a substrate composition. The buffer layer has a buffer layer composition. The buffer layer composition is substantially identical to the substrate composition. The presently disclosed methods further comprise epitaxially forming a heteroepitaxial layer on the buffer layer. The heteroepitaxial layer has a heteroepitaxial layer composition which is different from the substrate composition.