A device comprise a first semiconductor channel layer over a substrate, a second semiconductor channel layer over the first semiconductor channel layer, and source/drain epitaxial structures on opposite sides of the first semiconductor channel layer and opposite sides of the second semiconductor channel layer. A compressive strain in the second semiconductor channel layer is greater than a compressive strain in the first semiconductor channel layer. The source/drain epitaxial structures each comprise a first region interfacing the first semiconductor channel layer and a second region interfacing the second semiconductor channel layer, and the first region has a composition different from a composition of the second region.

Embodiments herein describe techniques, systems, and method for a semiconductor device. A nanowire transistor may include a channel region including a nanowire above a substrate, a source electrode coupled to a first end of the nanowire through a first etch stop layer, and a drain electrode coupled to a second end of the nanowire through a second etch stop layer. A gate electrode may be above the substrate to control conductivity in at least a portion of the channel region. A first spacer may be above the substrate between the gate electrode and the source electrode, and a second spacer may be above the substrate between the gate electrode and the drain electrode. A gate dielectric layer may be between the channel region and the gate electrode. Other embodiments may be described and/or claimed.

A method for forming a layer by cycled epitaxy includes at least one sequence of steps each having a first epitaxial deposition forming a first growth layer portion having a first thickness on a first monocrystalline pattern and a second growth layer portion having a second thickness on a second non-monocrystalline pattern, the second thickness being greater than the first thickness, and a second epitaxial deposition forming a first sacrificial layer portion having a third thickness on the first growth layer portion and a second sacrificial layer portion having a fourth thickness on the second growth layer portion. The first and second growth layer portions have an additional element content, greater than the additional element content present in the first and second sacrificial layer portions. The sequence also includes etching the whole of the third and fourth thicknesses and stopping before having consumed the whole of the first thickness.

Embodiments herein describe techniques, systems, and method for a semiconductor device. A nanowire transistor may include a channel region including a nanowire above a substrate, a source electrode coupled to a first end of the nanowire through a first etch stop layer, and a drain electrode coupled to a second end of the nanowire through a second etch stop layer. A gate electrode may be above the substrate to control conductivity in at least a portion of the channel region. A first spacer may be above the substrate between the gate electrode and the source electrode, and a second spacer may be above the substrate between the gate electrode and the drain electrode. A gate dielectric layer may be between the channel region and the gate electrode. Other embodiments may be described and/or claimed.

In a method, a first dielectric layer is formed over semiconductor fins, a second dielectric layer is formed over the first dielectric layer, the second dielectric layer is recessed below a top of each of the semiconductor fins, a third dielectric layer is formed over the recessed second dielectric layer, and the third dielectric layer is recessed below the top of the semiconductor fin, thereby forming a wall fin. The wall fin includes the recessed third dielectric layer and the recessed second dielectric layer disposed over the recessed third dielectric layer. The first dielectric layer is recessed below a top of the wall fin, a fin liner layer is formed, the fin liner layer is recessed and the semiconductor fins are recessed, and source/drain epitaxial layers are formed over the recessed semiconductor fins, respectively. The source/drain epitaxial layers are separated by the wall fin from each other.

Methods for depositing a silicon germanium tin boron (SiGeSn:B) film on a substrate are described. The method comprises exposing a substrate to a precursor mixture comprising a boron precursor, a silicon precursor, a germanium precursor, and a tin precursor to form a boron silicon germanium tin (SiGeSn:B) film on the substrate.

Disclosed is a method for manufacturing a power semiconductor device. The method includes forming a lower active layer on a substrate, forming an upper active layer on both sides of the lower active layer, forming a source electrode, a drain electrode, and a gate electrode on the upper active layer and the lower active layer, and forming a heat dissipating and electrical ground electrode penetrating the substrate and the lower active layer and connected to a lower surface of the lower active layer. The upper active layer may be epitaxially grown at a high doping concentration by a selective deposition method using a mask layer that exposes a portion of the lower active layer as a blocking layer.

In a method, a first dielectric layer is formed over semiconductor fins, a second dielectric layer is formed over the first dielectric layer, the second dielectric layer is recessed below a top of each of the semiconductor fins, a third dielectric layer is formed over the recessed second dielectric layer, and the third dielectric layer is recessed below the top of the semiconductor fin, thereby forming a wall fin. The wall fin includes the recessed third dielectric layer and the recessed second dielectric layer disposed over the recessed third dielectric layer. The first dielectric layer is recessed below a top of the wall fin, a fin liner layer is formed, the fin liner layer is recessed and the semiconductor fins are recessed, and source/drain epitaxial layers are formed over the recessed semiconductor fins, respectively. The source/drain epitaxial layers are separated by the wall fin from each other.

Devices comprising germanium nanosheets are described herein. Methods of forming such germanium nanosheets and devices including such germanium nanosheets are also described.

A method includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers over a substrate; forming a dummy gate structure across the fin structure; etching portions of the fin structure to expose portions of the substrate; forming source/drain stressors over the exposed portions of the substrate; after forming the source/drain stressors, removing the dummy gate structure; after removing the dummy gate structure, removing the first semiconductor layers such that the second semiconductor layers are suspended between the source/drain stressors; and forming a gate structure to surround each of the suspended second semiconductor layers. The source/drain stressors each comprise a first source/drain layer and a second source/drain layer over the first source/drain layer. An atomic concentration of a Group IV element or a Group V element in the second source/drain layer is greater than that in the first source/drain layer.