A method for making a multilayered device on an engineered substrate having a substrate coefficient of thermal expansion includes growing a buffer layer on the engineered substrate, and growing a first epitaxial layer on the buffer layer. The first epitaxial layer is characterized by an epitaxial coefficient of thermal expansion substantially equal to the substrate coefficient of thermal expansion.

A method for manufacturing a semiconductor structure is provided. The method includes a III-V semiconductor device in a first region of a base substrate and a further device in a second region of the base substrate. The method includes: (a) obtaining a base substrate comprising the first region and the second region, different from the first region; (b) providing a buffer layer over a surface of the base substrate at least in the first region, wherein the buffer layer comprises at least one monolayer of a first two-dimensional layered crystal material; (c) forming, over the buffer layer in the first region, and not in the second region, a III-V semiconductor material; and (d) forming, in the second region, at least part of the further device. A semiconductor structure is also provided.

A method of manufacturing nitride semiconductor substrate, comprising: providing silicon-on-insulator substrate which comprises an underlying silicon layer, a buried silicon dioxide layer and a top silicon layer; forming a first nitride semiconductor layer on the top silicon layer; forming, in the first nitride semiconductor layer, a plurality of notches which expose the top silicon layer; removing the top silicon layer and forming a plurality of protrusions and a plurality of recesses on an upper surface of the buried silicon dioxide layer, wherein each of the plurality of protrusions is in contact with the first nitride semiconductor layer, and there is a gap between each of the plurality of recesses and the first nitride semiconductor layer; and epitaxially growing a second nitride semiconductor layer on the first nitride semiconductor layer, such that the first nitride semiconductor layer and the second nitride semiconductor layer form a nitride semiconductor substrate.

An optoelectronic device grown on a miscut of GaN, wherein the miscut comprises a semi-polar GaN crystal plane (of the GaN) miscut x degrees from an m-plane of the GaN and in a c-direction of the GaN, where −15<x<−1 and 1<x<15 degrees.

A high electron mobility transistor includes: a first semiconductor layer over a substrate, and a second semiconductor layer over the first semiconductor layer, the second semiconductor layer having a band gap discontinuity with the first semiconductor layer, and at the first semiconductor layer and/or the second conductive layer includes indium. A top layer is over the second semiconductor layer, and a metal layer is over, and extends into, the top layer, the top layer separating the metal layer from the second semiconductor layer. A gate electrode is over the top layer, a third semiconductor layer being between the gate electrode and the top layer, where a sidewall of the third semiconductor layer and a sidewall of the metal layer are separated. A source and drain are on opposite sides of the gate electrode, the top layer extending continuously from below the source, below the gate electrode, and below the drain.

The disclosed technology generally relates to forming a thin film comprising titanium nitride (TiN), and more particularly to forming by a cyclical vapor deposition process the thin film comprising (TiN). In one aspect, a method of forming a thin film comprising TiN comprises exposing a semiconductor substrate to one or more first cyclical vapor deposition cycles each comprising an exposure to a first Ti precursor and an exposure to a first N precursor to form a first portion of the thin film and exposing the semiconductor substrate to one or more second cyclical vapor deposition cycles each comprising an exposure to a second Ti precursor and an exposure to a second N precursor to form a second portion of the thin film, wherein exposures to one or both of the first Ti precursor and the first N precursor during the one or more first cyclical vapor deposition cycles are at different pressures relative to corresponding exposures to one or both of the second Ti precursor and the second N precursor during the one or more second cyclical vapor deposition cycles. Aspects are also directed to semiconductor structures incorporating the thin film and method of forming the same.

A compound semiconductor has a high electron concentration of 5×10.sup.19 cm.sup.−3 or higher, exhibits an electron mobility of 46 cm.sup.2/V.Math.s or higher, and exhibits a low electric resistance, and thus is usable to produce a high performance semiconductor device. The present invention provides a group 13 nitride semiconductor of n-type conductivity that may be formed as a film on a substrate having a large area size at a temperature of room temperature to 700° C.

A device includes a diode that includes a first group III-nitride (III-N) material and a transistor adjacent to the diode, where the transistor includes the first III-N material. The diode includes a second III-N material, a third III-N material between the first III-N material and the second III-N material, a first terminal including a metal in contact with the third III-N material, a second terminal coupled to the first terminal through the first group III-N material. The device further includes a transistor structure, adjacent to the diode structure. The transistor structure includes the first, second, and third III-N materials, a source and drain, a gate electrode and a gate dielectric between the gate electrode and each of the first, second and third III-N materials.

This disclosure relates to methods of growing crystalline layers on amorphous substrates by way of an ultra-thin seed layer, methods for preparing the seed layer, and compositions comprising both. In an aspect of the invention, the crystalline layers can be thin films. In a preferred embodiment, these thin films can be free-standing.

The present invention relates to various high quality n-type and p-type doped gallium-based semiconductor materials, electronic components incorporating these materials, and processes of producing these materials. In particular, The present invention relates processes to achieve high quality, uniform doping of a whole wafer or a thin layer of gallium-based semiconductor materials for various applications such as a vertical power transistor or diode.