A method of fabricating a device involves forming a plurality of structures, such that each structure of the plurality includes a substrate and an epitaxial layer on the substrate. The epitaxial layer and the substrate have a lattice mismatch. The method further includes forming an electrical contact on the epitaxial layer of a selected structure of the plurality of structures and performing a current leakage measurement quality control test for the selected structure of the plurality of structures through the electrical contact. The method also involves forming a device on each of the remaining structures of the plurality of structures if the selected structure passed the leakage measurement quality control test or discarding each of the remaining structures of the plurality of structures if the selected structure did not pass the leakage measurement quality control test.

Implementations of the present disclosure generally relate to one or more flow ratio controllers and one or more gas injection inserts in the semiconductor processing chamber. In one implementation, an apparatus includes a first flow ratio controller including a first plurality of flow controllers, a second flow ratio controller including a second plurality of flow controllers, and a gas injection insert including a first portion and a second portion. The first portion includes a first plurality of channels and the second portion includes a second plurality of channels. The apparatus further includes a plurality of gas lines connecting the first and second pluralities of flow controllers to the first and second pluralities of channels. One or more gas lines of the plurality of gas lines are each connected to a channel of the first plurality of channels and a channel of the second plurality of channels.

A wafer carrier includes a pocket sized and shaped to accommodate a wafer, the pocket having a base and a substantially circular perimeter, and a removable orientation marker, the removable orientation marker comprising an outer surface and an inner surface, the outer surface having an arcuate form sized and shaped to mate with the substantially circular perimeter of the pocket, and the inner surface comprising a flat face, wherein the removable orientation marker further comprises a notch at a first end of the flat face.

A method of depositing a material on a substrate is provided. The method includes generating a plasma remote from one or more sputter targets suitable for plasma sputtering, wherein at least one distinct region of the one or more targets includes an alkali metal, alkaline earth metal, alkali metal containing compound, alkaline earth metal containing compound or a combination thereof; generating sputtered material from the target or targets using the plasma; and depositing the sputtered material on the substrate, the working distance between the target and the substrate being within +/−50% of the theoretical mean free path of the system.

A semiconductor device includes: a compound semiconductor layer having a first compound semiconductor layer and a second compound semiconductor layer having a higher melting point than the first compound semiconductor layer; and an insulation gate on the second compound semiconductor layer. The compound semiconductor layer further includes: a drift region; a source region; and a body region between the drift region and the source region. The insulation gate faces the body region. The body region bridges over both the first compound semiconductor layer and the second compound semiconductor layer.

A manufacturing method of a nitride semiconductor device includes: introducing a p type impurity into at least a part of an upper layer portion of a first nitride semiconductor layer to form a p type impurity introduction region; forming a second nitride semiconductor layer from an upper surface of the first nitride semiconductor layer so as to include the p type impurity introduction region; and performing an anneal treatment in a state where the second nitride semiconductor layer is formed on the first nitride semiconductor layer.

An exemplary embodiment of the present disclosure provides a method of fabricating a semiconductor device, comprising: providing a substrate, the substate comprising a base layer and two or more planar heteroepitaxial layers deposited on the base layer, the two or more heteroepitaxial layers comprising a first epitaxial layer having a first lattice constant and a second epitaxial layer having a second lattice constant different than the first lattice constant; etching the substrate to form one or more mesas; and depositing one or more non-planar overgrowth layers on the etched substrate.

According to the present disclosure, techniques related to manufacturing and applications of power photodiode structures and devices based on group-III metal nitride and gallium-based substrates are provided. More specifically, embodiments of the disclosure include techniques for fabricating photodiode devices comprising one or more of GaN, AlN, InN, InGaN, AlGaN, and AlInGaN, structures and devices. Such structures or devices can be used for a variety of applications including optoelectronic devices, photodiodes, power-over-fiber receivers, and others.

Devices for photoelectrodes for water splitting based on indium nanowires on flexible substrates as well as methods of manufacture by transferring nanowire arrays to flexible substrates.

Embodiments herein describe techniques for a semiconductor device over a semiconductor substrate. A first bonding layer is above the semiconductor substrate. One or more nanowires are formed above the first bonding layer to be a channel layer. A gate electrode is around a nanowire, where the gate electrode is in contact with the first bonding layer and separated from the nanowire by a gate dielectric layer. A source electrode or a drain electrode is in contact with the nanowire, above a bonding area of a second bonding layer, and separated from the gate electrode by a spacer, where the second bonding layer is above and in direct contact with the first bonding layer.