A method for forming nanostructures including introducing a hollow shell into a reactor. The hollow shell has catalyst nanoparticles exposed on its interior surface. The method also includes introducing a precursor into the reactor to grow nanostructures from the interior surface of the hollow shell from the catalyst nanoparticles.

An embodiment includes a III-V material based device, comprising: a first III-V material based buffer layer on a silicon substrate; a second III-V material based buffer layer on the first III-V material based buffer layer, the second III-V material including aluminum; and a III-V material based device channel layer on the second III-V material based buffer layer. Another embodiment includes the above subject matter and the first and second III-V material based buffer layers each have a lattice parameter equal to the III-V material based device channel layer. Other embodiments are included herein.

A semiconductor device includes a substrate comprising a layer made of Ge and a semiconductor multilayer structure grown on the layer made of Ge. The semiconductor multilayer structure includes at least one first layer comprising a material selected from a group consisting of Al.sub.xGa.sub.1-xAs, Al.sub.xGa.sub.1-x-yIn.sub.yAs, Al.sub.xGa.sub.1-x-yIn.sub.yAs.sub.1-zP.sub.z, Al.sub.xGa.sub.1-x-yIn.sub.yAs.sub.1-zN.sub.z, and Al.sub.xGa.sub.1-x-yIn.sub.yAs.sub.1-z-cN.sub.zP.sub.c, Al.sub.xGa.sub.1-x-yIn.sub.yAs.sub.1-z-cN.sub.zSb.sub.c, and Al.sub.xGa.sub.1-x-yIn.sub.yAs.sub.1-z-cP.sub.zSb.sub.c, wherein for any material a sum of the contents of all group-III elements equals 1 and a sum of the contents of all group-V elements equals 1. The semiconductor multilayer structure also includes at least one second layer comprising a material selected from a group consisting of GaInAsNSb, GaInAsN, AlGaInAsNSb, AlGaInAsN, GaAs, GaInAs, GaInAsSb, GaInNSb, GaInP, GaInPNSb, GaInPSb, GaInPN, AlInP, AlInPNSb, AlInPN, AlInPSb, AlGaInP, AlGaInPNSb, AlGaInPN, AlGaInPSb, GaInAsP, GaInAsPNSb, GaInAsPN, GaInAsPSb, GaAsP, GaAsPNSb, GaAsPN, GaAsPSb, AlGaInAs and AlGaAs.

A method of forming the fin structure that includes forming a replacement gate structure on a channel region of the at least one replacement fin structure; and forming an encapsulating dielectric encapsulating the replacement fin structure leaving a portion of the replacement gate structure exposed. The exposed portion of the replacement gate structure is etched to provide an opening through the encapsulating dielectric to the replacement fin structure. The replacement fin structure is etched selectively to the dielectric to provide a fin opening having a geometry dictated by the encapsulating dielectric. Functional fin structures of a second semiconductor material is epitaxially grown on the growth surface of the substrate substantially filling the fin opening.

Gallium-containing semiconductor layers are grown on a substrate, followed by dry etching of the gallium-containing semiconductor layers during fabrication of a device. After the dry etching, surface treatments are performed to remove damage from the sidewalls of the device. After the surface treatments, dielectric materials are deposited on the sidewalls of the device to passivate the sidewalls of the device. These steps result in an improvement in forward current-voltage characteristics and reduction in leakage current of the device, as well as an enhancement of light output power and efficiency of the device.

A method for forming a semiconductor device includes depositing an epitaxial layer on a semiconductor substrate, forming an oxygen diffusion region within the epitaxial layer by oxygen diffusion from the semiconductor substrate into a part of the epitaxial layer and tempering at least the oxygen diffusion region of the epitaxial layer at a temperature between 400° C. and 480° C. for more than 15 minutes.

An integrated circuit die includes a quad-gate device nanowire of channel material for a transistor (e.g., single material or stack to be a channel of a MOS device) formed by removing a portion of a sub-fin material from below the channel material, where the sub-fin material was grown in an aspect ration trapping (ART) trench. In some cases, in the formation of such nanowires, it is possible to remove the defective fin material or area under the channel. Such removal isolates the fin channel, removes the fin defects and leakage paths, and forms the nanowire of channel material having four exposed surfaces upon which gate material may be formed.

A method for fabrication a field-effect-transistor includes forming a plurality of fin structures on a substrate, forming a gate structure across each fin structure and covering a portion of top and sidewall surfaces of the fin structure, forming a first doped layer, made of a first semiconductor material and doped with first doping ions, in each fin structure on one side of the corresponding gate structure, and forming a second doped layer, made of a second semiconductor material, doped with second doping ions, and having doping properties different from the first doped layer, in each fin structure on another side of the corresponding gate structure.

The present invention relates to a method of manufacturing semiconductor materials comprising interface layers of group III-V materials in combination with Si substrates. Especially the present invention is related to a method of manufacturing semiconductor materials comprising GaAs in combination with Si(111) substrates, wherein residual strain due to different thermal expansion coefficient of respective materials is counteracted by introducing added layer(s) compensating the residual strain.

Systems and methods described herein may include a first semiconductor layer with a first lattice constant, a rare earth pnictide buffer epitaxially grown over the first semiconductor, wherein a first region of the rare earth pnictide buffer adjacent to the first semiconductor has a net strain that is less than 1%, a second semiconductor layer epitaxially grown over the rare earth pnictide buffer, wherein a second region of the rare earth pnictide buffer adjacent to the second semiconductor has a net strain that is a desired strain, and wherein the rare earth pnictide buffer may comprise one or more rare earth elements and one or more Group V elements. In some examples, the desired strain is approximately zero.