A method for forming a material having a Perovskite single crystal structure includes alternately growing, on a substrate, each of a plurality of first layers and each of a plurality of second layers having compositions different from the plurality of first layers and forming a material having a Perovskite single crystal structure by annealing the plurality of first layers and the plurality of second layers.

Embodiments of the invention generally relate processes for epitaxial growing Group III/V materials at high growth rates, such as about 30 μm/hr or greater, for example, about 40 μm/hr, about 50 μm/hr, about 55 μm/hr, about 60 μm/hr, or greater. The deposited Group III/V materials or films may be utilized in solar, semiconductor, or other electronic device applications. In some embodiments, the Group III/V materials may be formed or grown on a sacrificial layer disposed on or over the support substrate during a vapor deposition process. Subsequently, the Group III/V materials may be removed from the support substrate during an epitaxial lift off (ELO) process. The Group III/V materials are thin films of epitaxially grown layers which contain gallium arsenide, gallium aluminum arsenide, gallium indium arsenide, gallium indium arsenide nitride, gallium aluminum indium phosphide, phosphides thereof, nitrides thereof, derivatives thereof, alloys thereof, or combinations thereof.

Semiconductor devices are provided which comprise III-V FINFET devices that are formed with different semiconductor fin widths to obtain different threshold voltages, as well as methods for fabricating such III-V FINFET devices. For example, a semiconductor device comprises first and second semiconductor fins, which are formed of a III-V compound semiconductor material, and which have a first width W1 and a second width W2, respectively, wherein W1 is less than W2. First and second gate structures of first and second FINFET devices are formed over a portion of the first and second semiconductor fins, respectively. The first FINFET device comprises a first threshold voltage and the second FINFET device comprises a second threshold voltage. The first threshold voltage is greater than the second threshold voltage as a result of the first width W1 being less than the second width W2.

Semiconductor devices including a subfin including a first III-V compound semiconductor and a channel including a second III-V compound semiconductor are described. In some embodiments the semiconductor devices include a substrate including a trench defined by at least two trench sidewalls, wherein the first III-V compound semiconductor is deposited on the substrate within the trench and the second III-V compound semiconductor is epitaxially grown on the first III-V compound semiconductor. In some embodiments, a conduction band offset between the first III-V compound semiconductor and the second III-V compound semiconductor is greater than or equal to about 0.3 electron volts. Methods of making such semiconductor devices and computing devices including such semiconductor devices are also described.

A semiconductor substrate, comprising a first semiconductor material, is provided and an insulating layer is formed thereon; an opening is formed in the insulating layer. Thereby, a seed surface of the substrate is exposed. The opening has sidewalls and a bottom and the bottom corresponds to the seed surface of the substrate. A cavity structure is formed above the insulating layer, including the opening and a lateral growth channel extending laterally over the substrate. A matching array is grown on the seed surface of the substrate, including at least a first semiconductor matching structure comprising a second semiconductor material and a second semiconductor matching structure comprising a third semiconductor material. The compound semiconductor structure comprising a fourth semiconductor material is grown on a seed surface of the second matching structure. The first through fourth semiconductor materials are different from each other. Corresponding semiconductor structures are also included.

Atomic layer deposition (ALD) processes for forming Group VA element containing thin films, such as Sb, Sb—Te, Ge—Sb and Ge—Sb—Te thin films are provided, along with related compositions and structures. Sb precursors of the formula Sb(SiR.sup.1R.sup.2R.sup.3).sub.3 are preferably used, wherein R.sup.1, R.sup.2, and R.sup.3 are alkyl groups. As, Bi and P precursors are also described. Methods are also provided for synthesizing these Sb precursors. Methods are also provided for using the Sb thin films in phase change memory devices.

Methods and structures includes providing a substrate, forming a prelayer over a substrate, forming a barrier layer over the prelayer, and forming a channel layer over the barrier layer. Forming the prelayer may include growing the prelayer at a graded temperature. Forming the barrier layer is such that the barrier layer may include GaAs or InGaAs. Forming the channel layer is such that the channel layer may include InAs or an Sb-based heterostructure. Thereby structures are formed.

A method for forming III-N structures of desired nanoscale dimensions is disclosed. The method is based on, first, providing a material to serve as a shell inside which a cavity can be formed, followed by using epitaxial growth to fill the cavity with III-N semiconductor(s). Filling a cavity of specified shape and dimensions with a III-N semiconductor results in formation of a III-N structure which has shape and dimensions defined by those of the cavity in the shell, advantageously enabling formation of III-N structures on a nanometer scale without having to rely on etching of III-N materials. Ensuring that at least a part of the III-N material in the cavity is formed by lateral epitaxial overgrowth allows obtaining high quality III-N semiconductor in that part without having to grow a thick layer. Disclosed III-N nanostructures can serve as foundation for fabricating III-N device components, e.g. III-N transistors, having non-planar architecture.

A semiconductor structure and method for manufacturing thereof are provided. The semiconductor structure includes a silicon substrate having a first surface, a III-V layer on the first surface of the silicon substrate and over a first active region, and an isolation region in a portion of the III-V layer extended beyond the first active region. The first active region is in proximal to the first surface. The method includes the following operations. A silicon substrate having a first device region and a second device region is provided, a first active region is defined in the first device region, a III-V layer is formed on the silicon substrate, an isolation region is defined across a material interface in the layer by an implantation operation, and an interconnect penetrating through the isolation region is formed.

The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a replacement channel composed of a III-V compound semiconductor material in a doped layer of a III-V compound semiconductor substrate. The replacement channel may be formed by removing a portion of the doped layer located directly below a dummy gate stack that has been removed. A III-V compound semiconductor material may be grown in the removed the portion to form the replacement channel and a gate stack may be formed on the replacement channel.