Patent classifications
H01L21/02549
SOI substrate manufacturing method and SOI substrate
An SOI substrate manufacturing method and an SOI substrate are provided, where the method includes: forming a patterned etch-stop layer in an oxide layer of a first silicon substrate, bonding a surface, having the patterned etch-stop layer (130), of the first silicon substrate with a surface of a second silicon substrate, and peeling off a part of the first silicon substrate to form a patterned SOI substrate.
SYNTHESIS AND USE OF PRECURSORS FOR ALD OF GROUP VA ELEMENT CONTAINING THIN FILMS
Atomic layer deposition (ALD) processes for forming Group VA element containing thin films, such as Sb, SbTe, GeSb and GeSbTe thin films are provided, along with related compositions and structures. Sb precursors of the formula Sb(SiR.sup.1R.sup.2R.sup.3).sub.3 are preferably used, wherein R.sup.1, R.sup.2, and R.sup.3 are alkyl groups. As, Bi and P precursors are also described. Methods are also provided for synthesizing these Sb precursors. Methods are also provided for using the Sb thin films in phase change memory devices.
SEMICONDUCTOR CRYSTAL SUBSTRATE, INFRARED DETECTOR, METHOD FOR PRODUCING SEMICONDUCTOR CRYSTAL SUBSTRATE, AND METHOD FOR PRODUCING INFRARED DETECTOR
A semiconductor crystal substrate includes a crystal substrate that is formed of a material including one of GaSb and InAs, a first buffer layer that is formed on the crystal substrate and formed of a material including GaSb, and a second buffer layer that is formed on the first buffer layer and formed of a material including GaSb. The first buffer layer has a p-type conductivity, and the second buffer layer has an n-type conductivity.
P-N junction based devices with single species impurity for P-type and N-type doping
A technique relates to a semiconductor device. A bipolar transistor includes an emitter layer and a base layer, where the emitter layer and the base layer are doped with an impurity, the impurity being a same for the emitter and base layers. The bipolar transistor includes a collector layer.
Semiconductor crystal substrate, infrared detector, method for producing semiconductor crystal substrate, and method for producing infrared detector
A semiconductor crystal substrate includes a crystal substrate that is formed of a material including one of GaSb and InAs, a first buffer layer that is formed on the crystal substrate and formed of a material including GaSb, and a second buffer layer that is formed on the first buffer layer and formed of a material including GaSb. The first buffer layer has a p-type conductivity, and the second buffer layer has an n-type conductivity.
SEMICONDUCTOR LAMINATE AND LIGHT-RECEIVING ELEMENT
A semiconductor laminate includes a substrate composed of InP, a first buffer layer composed of InP containing less than 110.sup.21 cm.sup.3 Sb and disposed on the substrate, and a second buffer layer composed of InGaAs and disposed on the first buffer layer. The first buffer layer includes a first layer that has a higher concentration of Sb than the substrate and that is arranged to include a first main surface which is a main surface of the first buffer layer on the substrate side. The second buffer layer includes a second layer that has a lower concentration of Sb than the first layer and that is arranged to include a second main surface which is a main surface of the second buffer layer on the first buffer layer side.
VAPOR PHASE GROWTH DEVICE, AND EPI WAFER PRODUCING METHOD
A vapor phase growth device includes a flow channel defining a space through which a source gas for forming an epi layer flows, a susceptor configured to hold a substrate in a state where the substrate faces the space, and a first member disposed vertically above and opposite to the susceptor, the first member having a thermal expansion coefficient not less than 0.7 times and not more than 1.3 times the thermal expansion coefficient of the substrate. The flow channel includes a holding portion configured to hold the first member.
P-N JUNCTION BASED DEVICES WITH SINGLE SPECIES IMPURITY FOR P-TYPE AND N-TYPE DOPING
A technique relates to a semiconductor device. A bipolar transistor includes an emitter layer and a base layer, where the emitter layer and the base layer are doped with an impurity, the impurity being a same for the emitter and base layers. The bipolar transistor includes a collector layer.
NITRIDE SEMICONDUCTOR CRYSTAL AND METHOD OF FABRICATING THE SAME
Fabricating a high-quality nitride semiconductor crystal at a lower temperature. A nitride semiconductor crystal is fabricated by supplying onto a substrate (105) a group III element and/or a compound thereof, a nitrogen element and/or a compound thereof and an Sb element and/or a compound thereof, all of which serve as materials, and thereby vapor-growing at least one layer of nitride semiconductor film (104). A supply ratio of the Sb element to the nitrogen element in a growth process of the at least one layer of the nitride semiconductor film (104) is set to not less than 0.004.
FINFET transistor having a tapered subfin structure
An apparatus is described. The apparatus includes a FINFET transistor. The FINFET transistor comprises a tapered subfin structure having a sidewall surface area that is large enough to induce aspect ratio trapping of lattice defects along sidewalls of the subfin structure so that the defects are substantially prevented from reaching said FINFET transistor's channel.