H01L21/02554

Semiconductor device and method for manufacturing the same

A more convenient and highly reliable semiconductor device which has a transistor including an oxide semiconductor with higher impact resistance used for a variety of applications is provided. A semiconductor device has a bottom-gate transistor including a gate electrode layer, a gate insulating layer, and an oxide semiconductor layer over a substrate, an insulating layer over the transistor, and a conductive layer over the insulating layer. The insulating layer covers the oxide semiconductor layer and is in contact with the gate insulating layer. In a channel width direction of the oxide semiconductor layer, end portions of the gate insulating layer and the insulating layer are aligned with each other over the gate electrode layer, and the conductive layer covers a channel formation region of the oxide semiconductor layer and the end portions of the gate insulating layer and the insulating layer and is in contact with the gate electrode layer.

METHODS AND MATERIAL DEPOSITION SYSTEMS FOR FORMING SEMICONDUCTOR LAYERS
20230187206 · 2023-06-15 · ·

In embodiments, an optoelectronic device comprises a substrate formed of magnesium oxide, and a multi-region stack epitaxially deposited upon the substrate. The multi-region stack may comprise a non-polar crystalline material structure along a growth direction, or may comprise a crystal polarity having an oxygen-polar crystal structure or a metal-polar crystal structure along the growth direction. In some cases, at least one region of the multi-region stack is a bulk semiconductor material comprising Mg.sub.(x)Zn.sub.(1-x)O. In some cases, at least one region of the multi-region stack is a superlattice comprising MgO and Mg.sub.(x)Zn.sub.(1-x)O.

Superlattice films for photonic and electronic devices

Superlattices and methods of making them are disclosed herein. The superlattices are prepared by irradiating a sample to prepare an alternating superlattice of layers of a first material and a second material, wherein the ratio of the first deposition rate to the second deposition rate is between 1.0:2.0 and 2.0:1.0. The superlattice comprises a multiplicity of alternating layers, wherein the multiplicity of layers of the first material have a thickness between 0.1 nm and 50.0 nm or the multiplicity of layers of the second material have a thickness between 0.1 nm and 50.0.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
20230022290 · 2023-01-26 ·

A more convenient and highly reliable semiconductor device which has a transistor including an oxide semiconductor with higher impact resistance used for a variety of applications is provided. A semiconductor device has a bottom-gate transistor including a gate electrode layer, a gate insulating layer, and an oxide semiconductor layer over a substrate, an insulating layer over the transistor, and a conductive layer over the insulating layer. The insulating layer covers the oxide semiconductor layer and is in contact with the gate insulating layer. In a channel width direction of the oxide semiconductor layer, end portions of the gate insulating layer and the insulating layer are aligned with each other over the gate electrode layer, and the conductive layer covers a channel formation region of the oxide semiconductor layer and the end portions of the gate insulating layer and the insulating layer and is in contact with the gate electrode layer.

Advanced electronic device structures using semiconductor structures and superlattices

Semiconductor structures and methods for forming those semiconductor structures are disclosed. For example, a semiconductor structure with a p-type superlattice region, an i-type superlattice region, and an n-type superlattice region is disclosed. The semiconductor structure can have a polar crystal structure with a growth axis that is substantially parallel to a spontaneous polarization axis of the polar crystal structure. In some cases, there are no abrupt changes in polarisation at interfaces between each region. At least one of the p-type superlattice region, the i-type superlattice region and the n-type superlattice region can comprise a plurality of unit cells exhibiting a monotonic change in composition from a wider band gap (WBG) material to a narrower band gap (NBG) material or from a NBG material to a WBG material along the growth axis to induce p-type or n-type conductivity.

SPUTTERING TARGET, OXIDE SEMICONDUCTOR, OXYNITRIDE SEMICONDUCTOR, AND TRANSISTOR
20230013303 · 2023-01-19 ·

A novel oxide semiconductor, a novel oxynitride semiconductor, a transistor including them, or a novel sputtering target is provided. A composite target includes a first region and a second region. The first region includes an insulating material and the second region includes a conductive material. The first region and the second region each include a microcrystal whose diameter is greater than or equal to 0.5 nm and less than or equal to 3 nm or a value in the neighborhood thereof. A semiconductor film is formed using the composite target.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device which has favorable electrical characteristics, a method for manufacturing a semiconductor device with high productivity, and a method for manufacturing a semiconductor device with a high yield are provided. The method for manufacturing a semiconductor device includes a first step of forming a first insulating layer containing silicon and nitrogen, a second step of adding oxygen in a vicinity of a surface of the first insulating layer, a third step of forming a semiconductor layer containing a metal oxide over and in contact with the first insulating layer, a fourth step of forming a second insulating layer containing oxygen over and in contact with the semiconductor layer, a fifth step of performing plasma treatment in an atmosphere containing oxygen at a first temperature, a sixth step of performing plasma treatment in an atmosphere containing oxygen at a second temperature lower than the first temperature, and a seventh step of forming a third insulating layer containing silicon and nitrogen over the second insulating layer.

SEMICONDUCTOR DEVICE
20230027596 · 2023-01-26 ·

A wiring structure includes a structure body including a pattern, a first conductive layer above the structure body, the first conductive layer having a shape, the shape crossing an edge of a pattern of the structure body and reflecting a step of the edge of the pattern of the structure body, a first insulating layer above the first conductive layer, the first insulating layer having a first opening overlapping the edge of the pattern of the structure body in a plane view, and r is arranged with a second opening in a region overlapping the semiconductor layer in a plane view, a second conductive layer in the first opening, the second conductive layer being connected to the first conductive layer.

Semiconductor device and manufacturing method thereof

A semiconductor device which includes a thin film transistor having an oxide semiconductor layer and excellent electrical characteristics is provided. Further, a method for manufacturing a semiconductor device in which plural kinds of thin film transistors of different structures are formed over one substrate to form plural kinds of circuits and in which the number of steps is not greatly increased is provided. After a metal thin film is formed over an insulating surface, an oxide semiconductor layer is formed thereover. Then, oxidation treatment such as heat treatment is performed to oxidize the metal thin film partly or entirely. Further, structures of thin film transistors are different between a circuit in which emphasis is placed on the speed of operation, such as a logic circuit, and a matrix circuit.

METAL OXIDE FILM AND METHOD FOR FORMING METAL OXIDE FILM

A metal oxide film including a crystal part and having highly stable physical properties is provided. The size of the crystal part is less than or equal to 10 nm, which allows the observation of circumferentially arranged spots in a nanobeam electron diffraction pattern of the cross section of the metal oxide film when the measurement area is greater than or equal to 5 nmφ and less than or equal to 10 nmφ.