Methods for producing the amorphous metal oxide semiconductor layer where amorphous metal oxide semiconductor layer is formed by use of a precursor composition containing a metal salt, a primary amide, and a water-based solution. The methodology for producing the amorphous metal oxide semiconductor layer includes applying the precursor composition onto a substrate to form a precursor film, and firing the film at a temperature of 150° C. or higher and lower than 300° C.

A vertical field effect transistor according to an embodiment of the present invention does not require a spacer and, accordingly, remarkably alleviates the problem that electric charge is scattered at an interface, thereby having excellent electrical characteristics. The vertical field effect transistor includes a substrate, a source electrode positioned on the substrate, an active layer positioned on the source electrode and having vertically grown crystal grains, a drain electrode positioned on the active layer to be spaced by the active layer away from the source electrode, a gate insulating layer positioned on a lateral surface of the active layer, and a gate electrode positioned on the gate insulating layer.

Methods of forming indium gallium zinc oxide (IGZO) films by vapor deposition are provided. The IGZO films may, for example, serve as a channel layer in a transistor device. In some embodiments atomic layer deposition processes for depositing IGZO films comprise an IGZO deposition cycle comprising alternately and sequentially contacting a substrate in a reaction space with a vapor phase indium precursor, a vapor phase gallium precursor, a vapor phase zinc precursor and an oxygen reactant. In some embodiments the ALD deposition cycle additionally comprises contacting the substrate with an additional reactant comprising one or more of NH.sub.3, N.sub.2O, NO.sub.2 and H.sub.2O.sub.2.

Semiconductor structures and methods for forming those semiconductor structures are disclosed. For example, a semiconductor structure with a p-type superlattice region, an i-type superlattice region, and an n-type superlattice region is disclosed. The semiconductor structure can have a polar crystal structure with a growth axis that is substantially parallel to a spontaneous polarization axis of the polar crystal structure. In some cases, there are no abrupt changes in polarisation at interfaces between each region. At least one of the p-type superlattice region, the i-type superlattice region and the n-type superlattice region can comprise a plurality of unit cells exhibiting a monotonic change in composition from a wider band gap (WBG) material to a narrower band gap (NBG) material or from a NBG material to a WBG material along the growth axis to induce p-type or n-type conductivity.

A more convenient and highly reliable semiconductor device which has a transistor including an oxide semiconductor with higher impact resistance used for a variety of applications is provided. A semiconductor device has a bottom-gate transistor including a gate electrode layer, a gate insulating layer, and an oxide semiconductor layer over a substrate, an insulating layer over the transistor, and a conductive layer over the insulating layer. The insulating layer covers the oxide semiconductor layer and is in contact with the gate insulating layer. In a channel width direction of the oxide semiconductor layer, end portions of the gate insulating layer and the insulating layer are aligned with each other over the gate electrode layer, and the conductive layer covers a channel formation region of the oxide semiconductor layer and the end portions of the gate insulating layer and the insulating layer and is in contact with the gate electrode layer.

A novel deposition method of a metal oxide is provided. The deposition method includes a first step of supplying a first precursor to a chamber; a second step of supplying a second precursor to the chamber; a third step of supplying a third precursor to the chamber; and a fourth step of introducing an oxidizer into the chamber after the first step, the second step, and the third step. The first to third precursors are different kinds of precursors, and a substrate placed in the chamber in the first to fourth steps is heated to a temperature higher than or equal to 300° C. and lower than or equal to decomposition temperatures of the first to third precursors.

A semiconductor device with low parasitic capacitance is provided. The semiconductor device includes a first oxide insulator, an oxide semiconductor, a second oxide insulator, a gate insulating layer, a gate electrode layer, source and drain electrode layers and an insulating layer. The oxide semiconductor includes first to fifth regions. The first region overlaps with the source electrode layer. The second region overlaps with the drain electrode layer. The third region overlaps with the gate electrode layer. The fourth region is between the first region and the third region. The fifth region is between the second region and the third region. The fourth region and the fifth region each contain an element N (N is hydrogen, nitrogen, helium, neon, argon, krypton, or xenon). A top surface of the insulating layer is positioned at a lower level than top surfaces of the source and drain electrode layers.

An oxide thin film transistor includes an oxide active layer, a first loose layer and a first oxygen release layer. The first loose layer is at least disposed on a first surface of the oxide active layer perpendicular to a thickness direction of the oxide active layer, and is in contact with the oxide active layer. A material of the first loose layer includes a first inorganic oxide insulating material. The first oxygen release layer is disposed on a surface of the first loose layer facing away from the oxide active layer, and is in contact with the first loose layer. A material of the first oxygen release layer is a first oxygen-containing insulating material.

A crystalline IZTO oxide semiconductor and a thin film transistor having the same are provided. The thin film transistor includes a gate electrode, a crystalline In—Zn—Sn oxide (IZTO) channel layer overlapping the upper or lower portions of the gate electrode and having hexagonal crystal grains, and a gate insulating layer disposed between the gate electrode and the IZTO channel layer, and source and drain electrodes respectively connected to both ends of the IZTO channel layer.

Various forms of Mg.sub.xGe.sub.1-xO.sub.2-x are disclosed, where the Mg.sub.xGe.sub.1-xO.sub.2-x are epitaxial layers formed on a substrate comprising a substantially single crystal substrate material. The epitaxial layer of Mg.sub.xGe.sub.1-xO.sub.2-x has a crystal symmetry compatible with the substrate material. Semiconductor structures and devices comprising the epitaxial layer of Mg.sub.xGe.sub.1-xO.sub.2-x are disclosed, along with methods of making the epitaxial layers and semiconductor structures and devices.