A method of manufacturing a solar cell including depositing a first electrode over a substrate under vacuum, depositing at least one p-type semiconductor absorber layer over the first electrode without breaking the vacuum, where the p-type semiconductor absorber layer comprises a copper indium selenide (CIS) based alloy material, sputter depositing an n-type semiconductor layer over the at least one p-type semiconductor absorber layer to form zinc oxysulfide in the n-type semiconductor layer without breaking the vacuum, and depositing a second electrode over the n-type semiconductor layer without breaking the vacuum.

Provided is method of manufacturing a conductive film. The method includes forming a conductive film including a plurality of flakes on a substrate, wherein the conductive film is a semiconductor or a conductor, and forming a passivation region selectively on a boundary between the flakes adjacent to each other. The passivation region includes a metal compound selected from the group consisting of metal chalcogenide and transition metal chalcogenide. The forming of the passivation region includes providing a solution containing a first precursor including a cation of the metal compound and a second precursor including an anion of the metal compound on the conductive film. pH of the solution is between 7.0 and 10.0.

Techniques for minimizing loss of volatile components during thermal processing of kesterite films are provided. In one aspect, a method for annealing a kesterite film is provided. The method includes: placing a cover over the kesterite film; and annealing the cover and the kesterite film such that, for an entire duration of the annealing, the cover is at a temperature T1 and the kesterite film is at a temperature T2, wherein the temperature T1 is greater than or equal to the temperature T2. Optionally, during a cool down segment of the annealing, conditions can be reversed to have the temperature T1 be less than the temperature T2. A solar cell and method for formation thereof using the present annealing techniques are also provided.

In some aspects, methods of forming a metal sulfide thin film are provided. According to some methods, a metal sulfide thin film is deposited on a substrate in a reaction space in a cyclical process where at least one cycle includes alternately and sequentially contacting the substrate with a first vapor-phase metal reactant and a second vapor-phase sulfur reactant. In some aspects, methods of forming a three-dimensional architecture on a substrate surface are provided. In some embodiments, the method includes forming a metal sulfide thin film on the substrate surface and forming a capping layer over the metal sulfide thin film. The substrate surface may comprise a high-mobility channel.

A sputter deposition system and method, the system including a process module containing a vacuum enclosure configured to receive a moving substrate, a first sputtering target disposed in the vacuum enclosure and including a target material, and a shield disposed between the first sputtering target and the substrate, the shield having upper and lower edges. At least a portion of each of the upper and lower edges is not parallel to a movement direction of the substrate past the first sputtering target.

A shielded sputter deposition system and method, the system including a process module including: a vacuum enclosure configured to receive a moving substrate, sputtering targets disposed in the vacuum enclosure, each sputtering target including a target material, and a peripheral shield disposed between the and substrate and an interstitial space located between adjacent sputtering targets. The peripheral shield may be configured to at least partially block indirect deposition of sputtered target material onto the substrate and to permit direct deposition of the sputtered target material onto the substrate.

Disclosed herein is a semiconducting nanoparticle comprising a one-dimensional semiconducting nanoparticle having a first end and a second end; where the second end is opposed to the first end; and two first endcaps, one of which contacts the first end and the other of which contacts the second end respectively of the one-dimensional semiconducting nanoparticle; where the first endcap that contacts the first end comprises a first semiconductor and where the first endcap extends from the first end of the one-dimensional semiconducting nanoparticle to form a first nanocrystal heterojunction; where the first endcap that contacts the second end comprises a second semiconductor; where the first endcap extends from the second end of the one-dimensional semiconducting nanoparticle to form a second nanocrystal heterojunction; and where the first semiconductor and the second semiconductor are chemically different from each other.

A method includes forming a gate dielectric layer over a gate electrode layer; forming a 2-D material layer over the gate dielectric layer; forming source/drain contacts over source/drain regions of the 2-D material layer, in which each of the source/drain contacts includes an antimonene layer and a metal layer over the antimonene layer; and after forming the source/drain contacts, removing a first portion of the 2-D material layer exposed by the source/drain contacts, while leaving a second portion of the 2-D material layer remaining over the gate dielectric layer as a channel region.

A method of manufacturing a semiconductor device includes forming a first layer of a first planarizing material over a patterned surface of a substrate, forming a second layer of a second planarizing material over the first planarizing layer, crosslinking a portion of the first planarizing material and a portion of the second planarizing material, and removing a portion of the second planarizing material that is not crosslinked. In an embodiment, the method further includes forming a third layer of a third planarizing material over the second planarizing material after removing the portion of the second planarizing material that is not crosslinked. The third planarizing material can include a bottom anti-reflective coating or a spin-on carbon, and an acid or an acid generator. The first planarizing material can include a spin-on carbon, and an acid, a thermal acid generator or a photoacid generator.

Two-dimensional (2D) materials and their heterostructures show a promising path for next generation electronics. Nevertheless, there are challenges with (i) controlling monolayer (ML)-by-ML 2D material growth, (ii) maintaining single-domain growth, and (iii) controlling the number of layers and crystallinity at the wafer-scale. The deterministic confined growth techniques disclosed here address these challenges simultaneously to produce wafer-scale single-domain 2D MLs and their heterostructures on arbitrary substrates. The growth of the first nuclei is confined by patterning SiO.sub.2 masks on 2-inch substrates to define selective or confined growth areas. Each growth area or trench is just a few microns wide and is filled with a single-domain ML before the second set of nuclei is introduced. Growing the second set of nuclei within the trenches yields an array of single-domain bilayers at the 2-inch wafer scale. Devices made with the single-domain bilayers exhibit excellent performance over the entire wafer.