A method of performing heteroepitaxy comprises exposing an OP-GaAs template in an HVPE reactor to a carrier gas, a first precursor gas, a second precursor gas (2pg), a Group II element, and a third precursor gas (3pg), to form an epitaxial growth of one of GaAs, GaP, and GaAsP directly on the OP-GaAs template; wherein the carrier gas is H.sub.2, wherein the first precursor is HCl, the Group II element is Ga; and wherein the second (V or VI group) precursor is one or more of AsH.sub.3 (arsine) and PH.sub.3 (phosphine), and the third precursor is one or more of PH.sub.3 and AsH.sub.3. For an epitaxial growth of GaAsP, the method may further comprise flowing the second and third precursors through the HVPE reactor at a 2pg:3pg ratio of about 1:0; heating the OP-template to 500° C.-900° C.; and gradually changing the 2pg:3pg ratio toward 0:1 over time.

A method of performing heteroepitaxy comprises exposing a substrate to a carrier gas, a first precursor gas, a Group II/III element, and a second precursor gas, to form a heteroepitaxial growth of one of GaAs, AlAs, InAs, GaP, InP, ZnSe, GaSe, CdSe, InSe, ZnTe, CdTe, GaTe, HgTe, GaSb, InSb, AlSb, CdS, GaN, and AlN on the substrate; wherein the substrate comprises one of GaAs, AlAs, InAs, GaP, InP, ZnSe, GaSe, CdSe, InSe, ZnTe, CdTe, GaTe, HgTe, GaSb, InSb, AlSb, CdS, GaN, and AlN; wherein the carrier gas is H.sub.2, wherein the first precursor is HCl, the Group II/III element comprises at least one of Zn, Cd, Hg, Al, Ga, and In; and wherein the second precursor is one of AsH.sub.3 (arsine), PH.sub.3 (phosphine), H.sub.2Se (hydrogen selenide), H.sub.2Te (hydrogen telluride), SbH.sub.3 (hydrogen antimonide), H.sub.2S (hydrogen sulfide), and NH.sub.3 (ammonia). The process may be an HVPE (hydride vapor phase epitaxy) process.

Production of a transistor, the channel structure of which comprises at least one finned channel structure, the method comprising: forming, from a substrate (1), a molding block (3), forming, on the molding block, a thin layer (7) made from a given semiconductor or semi-metallic material, and consisting of one to ten atomic or molecular monolayers of two-dimensional crystal, withdrawing the molding block while retaining a portion (7a) of the thin layer extending against a lateral face of the molding block, said retained portion (7a) forming a fin that is capable of forming a channel structure of the transistor, producing a coating gate electrode against said fin.

Provided is a thin film transistor including a source electrode, a drain electrode, and a channel layer connecting the source electrode and the drain electrode. The channel layer includes a tin-based oxide represented by SnMO, wherein M includes at least one of a non-metal chalcogen element or a halogen element.

Atomic layer deposition (ALD) processes for forming Te-containing thin films, such as Sb—Te, Ge—Te, Ge—Sb—Te, Bi—Te, and Zn—Te thin films are provided. ALD processes are also provided for forming Se-containing thin films, such as Sb—Se, Ge—Se, Ge—Sb—Se, Bi—Se, and Zn—Se thin films are also provided. Te and Se precursors of the formula (Te,Se)(SiR.sup.1R.sup.2R.sup.3).sub.2 are preferably used, wherein R.sup.1, R.sup.2, and R.sup.3 are alkyl groups. Methods are also provided for synthesizing these Te and Se precursors. Methods are also provided for using the Te and Se thin films in phase change memory devices.

A method for forming a semiconductor device having a lateral semiconductor heterojunction involves forming a first metal chalcogenide layer of the lateral semiconductor heterojunction adjacent to a first metal electrode on a substrate. The first metal chalcogenide layer includes a same metal as the first metal electrode and at least some of the first metal chalcogenide layer includes metal from the first metal electrode. A second metal chalcogenide layer of the lateral semiconductor heterojunction is formed adjacent to the first metal chalcogenide layer. A second metal electrode is formed adjacent to the second metal chalcogenide layer. The second metal chalcogenide layer includes a same metal as the second metal electrode.

A subtractive forming method that includes providing a material stack including a samarium and selenium containing layer and an aluminum containing layer in direct contact with the samarium and selenium containing layer. The samarium component of the samarium and selenium containing layer of the exposed portion of the material stack is etched with an etch chemistry comprising citric acid and hydrogen peroxide that is selective to the aluminum containing layer. The hydrogen peroxide reacts with the aluminum containing layer to provide an oxide etch protectant surface on the aluminum containing layer, and the citric acid etches samarium selectively to the oxide etch protectant surface. Thereafter, a remaining selenium component of is removed by elevating a temperature of the selenium component.

A method for forming a semiconductor device having a lateral semiconductor heterojunction involves forming a first metal chalcogenide layer of the lateral semiconductor heterojunction adjacent to a first metal electrode on a substrate. The first metal chalcogenide layer includes a same metal as the first metal electrode and at least some of the first metal chalcogenide layer includes metal from the first metal electrode. A second metal chalcogenide layer of the lateral semiconductor heterojunction is formed adjacent to the first metal chalcogenide layer. A second metal electrode is formed adjacent to the second metal chalcogenide layer. The second metal chalcogenide layer includes a same metal as the second metal electrode.

A method is described for preparing a nanorods assembly. The method comprises providing a mixture comprising at least a liquid crystal and nanorods and depositing said mixture on the surface of at least substrate. The method further comprises aligning said nanorods with their long axis of the nanorods along a preferred direction on said substrate resulting in a nanorods and liquid crystal assembly, said aligning being performed by applying an external alternating current electrical field.

A subtractive forming method for piezoresistive material stacks includes applying an etch chemistry to an exposed first portion of a piezoresistive material stack. The etch chemistry includes a citric acid component for removing a first element of a piezoelectric layer of the piezoresistive material stack selectively to a surface oxide. At least one second element of the piezoelectric layer remains. The method further includes heating the piezoresistive material stack after said applying the etch chemistry to vaporize the at least one second element. A second portion of the piezoresistive material stack is protected from the removal and the heating by a mask.