A subtractive forming method for piezoresistive material stacks includes applying an etch chemistry to an exposed first portion of a piezoresistive material stack. The etch chemistry includes a citric acid component for removing a first element of a piezoelectric layer of the piezoresistive material stack selectively to a surface oxide. At least one second element of the piezoelectric layer remains. The method further includes heating the piezoresistive material stack after said applying the etch chemistry to vaporize the at least one second element. A second portion of the piezoresistive material stack is protected from the removal and the heating by a mask.

Halometallate-capped semiconductor nanocrystals and methods for making the halometallate-capped semiconductor nanocrystals are provided. Also provided are methods of using solutions of the halometallate-capped semiconductor nanocrystals as precursors for semiconductor film formation. When solutions of the halometallate ligand-capped semiconductor nanocrystals are annealed, the halometallate ligands can act as grain growth promoters during the sintering of the semiconductor nanocrystals.

A sputter deposition system and method, the system including a process module containing a vacuum enclosure configured to receive a moving substrate, a first sputtering target disposed in the vacuum enclosure and including a target material, and a shield disposed between the first sputtering target and the substrate, the shield having upper and lower edges. At least a portion of each of the upper and lower edges is not parallel to a movement direction of the substrate past the first sputtering target.

A shielded sputter deposition system and method, the system including a process module including: a vacuum enclosure configured to receive a moving substrate, sputtering targets disposed in the vacuum enclosure, each sputtering target including a target material, and a peripheral shield disposed between the and substrate and an interstitial space located between adjacent sputtering targets. The peripheral shield may be configured to at least partially block indirect deposition of sputtered target material onto the substrate and to permit direct deposition of the sputtered target material onto the substrate.

Disclosed herein is a semiconducting nanoparticle comprising a one-dimensional semiconducting nanoparticle having a first end and a second end; where the second end is opposed to the first end; and two first endcaps, one of which contacts the first end and the other of which contacts the second end respectively of the one-dimensional semiconducting nanoparticle; where the first endcap that contacts the first end comprises a first semiconductor and where the first endcap extends from the first end of the one-dimensional semiconducting nanoparticle to form a first nanocrystal heterojunction; where the first endcap that contacts the second end comprises a second semiconductor; where the first endcap extends from the second end of the one-dimensional semiconducting nanoparticle to form a second nanocrystal heterojunction; and where the first semiconductor and the second semiconductor are chemically different from each other.

Two-dimensional (2D) materials and their heterostructures show a promising path for next generation electronics. Nevertheless, there are challenges with (i) controlling monolayer (ML)-by-ML 2D material growth, (ii) maintaining single-domain growth, and (iii) controlling the number of layers and crystallinity at the wafer-scale. The deterministic confined growth techniques disclosed here address these challenges simultaneously to produce wafer-scale single-domain 2D MLs and their heterostructures on arbitrary substrates. The growth of the first nuclei is confined by patterning SiO.sub.2 masks on 2-inch substrates to define selective or confined growth areas. Each growth area or trench is just a few microns wide and is filled with a single-domain ML before the second set of nuclei is introduced. Growing the second set of nuclei within the trenches yields an array of single-domain bilayers at the 2-inch wafer scale. Devices made with the single-domain bilayers exhibit excellent performance over the entire wafer.

Some embodiments include a method. The method can include: providing a carrier substrate; forming a first device material over the carrier substrate; and after forming the first device material over the carrier substrate, transforming the first device material into a second device material. Meanwhile, the transforming the first device material into the second device material can include: causing a cationic exchange in the first device material; and causing an anionic exchange in the first device material. The causing the cationic exchange in the first device material and the causing the anionic exchange in the first device material can occur approximately simultaneously. Other embodiments of related methods and systems are also disclosed.

A semiconductor crystal substrate includes: a crystal substrate whose principal surface is inclined relative to a (001) plane; and a superlattice structure layer including a first superlattice formation layer and a second superlattice formation layer, wherein the first superlattice formation layer is formed of Ga.sub.1-x1In.sub.x1As.sub.y1Sb.sub.1-y1 (0x10.1, 0y10.1), and a value of a standard deviation to a mean value of atomic step widths in an inclination direction is equal to or greater than 0 and equal to or smaller than 0.20, and the second superlattice formation layer is formed of Ga.sub.1-x2In.sub.x2As.sub.y2Sb.sub.1-y2 (0.9x21, 0.9y21), and a value of a standard deviation to a mean value of atomic step widths in an inclination direction is equal to or greater than 0 and equal to or smaller than 0.40.

The present invention generally relates to nanoscale wires, and to methods of producing nanoscale wires. In some aspects, the nanoscale wires are nanowires comprising a core which is continuous and a shell which may be continuous or discontinuous, and/or may have regions having different cross-sectional areas. In some embodiments, the shell regions are produced by passing the shell material (or a precursor thereof) over a core nanoscale wire under conditions in which Plateau-Raleigh crystal growth occurs, which can lead to non-homogenous deposition of the shell material on different regions of the core. The core and the shell each independently may comprise semiconductors, and/or non-semiconductor materials such as semiconductor oxides, metals, polymers, or the like. Other embodiments are generally directed to systems and methods of making or using such nanoscale wires, devices containing such nanoscale wires, or the like.

Atomic layer deposition (ALD) processes for forming Te-containing thin films, such as SbTe, GeTe, GeSbTe, BiTe, and ZnTe thin films are provided. ALD processes are also provided for forming Se-containing thin films, such as SbSe, GeSe, GeSbSe, BiSe, and ZnSe thin films are also provided. Te and Se precursors of the formula (Te,Se)(SiR.sup.1R.sup.2R.sup.3).sub.2 are preferably used, wherein R.sup.1, R.sup.2, and R.sup.3 are alkyl groups. Methods are also provided for synthesizing these Te and Se precursors. Methods are also provided for using the Te and Se thin films in phase change memory devices.